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US 6,552,361 B1Granted
Thin film transistor device
AssigneeIndustrial Technology Research Institute
InventorsI-Min Lu, Jr-Hong Chen
Life of this patent
Estimating the term…
Abstract
A thin film transistor (TFT) and method of fabricating the same. A planarization layer of polymer is formed on the interlayer to reduce short-circuit. The planarization layer further reduces the capacitance of the crossover capacitor and the delay time of the LCD panel using the TFT is therefor minimized. A gate thereof can be design under the data line to increase aperture ratio.
Claims13
A thin film transistor (TFT) device, comprising:
- a substrate;
- a source region over the substrate;
- a drain region over the substrate;
- an active layer over the substrate between the source region and the drain region;
- a gate insulating layer covering the source region, the drain region and the active layer;
- a gate on the gate insulating layer;
- an interlayer over the gate insulating layer, covering the gate;
- a planarization layer over the interlayer;
- a source region metal line on the planarization layer, wherein the source region metal line is connected to the source region;
- a drain region metal line on the planarization layer, wherein the drain region metal line is connected to the drain region;
- a passivation layer over the planarization layer, covering the source region metal line and the drain region metal line, wherein the gate insulating layer, the interlayer, and the planarization layer are formed between the substrate and the passivation layer;
- and
- a conductive layer on the passivation layer, connecting to the source region metal line.
10 more elements
A thin film transistor (TFT) device, comprising:
- a substrate;
- a source region over the substrate;
- a drain region over the substrate;
- an active layer over the substrate between the source region and the drain region;
- a gate insulating layer formed of a gate insulating material selected from the group of materials consisting of silicon oxide and silicon nitride, the gate insulating material of the gate insulating layer covering the source region, the drain region and the active layer;
- a gate on the gate insulating layer;
- an interlayer made of a polymer, provided over the gate insulating layer, covering the gate;
- a planarization layer over the interlayer;
- a source region metal line on the planarization layer, wherein the source region metal line is connected to the source region;
- a drain region metal line on the planarization layer, wherein the drain region metal line is connected to the drain region;
- a passivation layer over the planarization layer, covering the source region metal line and the drain region metal line, whereby the gate insulating layer, the interlayer, and the planarization layer are formed between the substrate and the passivation layer;
- and a conductive layer on the passivation layer, connecting to the source region metal line.
9 more elements
Dependencies are inferred from the claim text.