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AssigneeNEC Electronics Corporation
InventorsSouichirou Iguchi, Takayuki Watanabe, Junji Kiyono
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A trench isolation structure is fabricated on a silicon substrate by initially depositing a masking layer of nitride having an aperture. A spacer of oxide is then formed on the inner sidewall of the aperture to define a mask window. A trench is formed in the substrate by etching it through the mask window. The spacer is removed to form stepped shoulder portions on upper edges of the trench. A liner of thermal oxide is provided in the trench, followed by deposition of a liner of nitride on an area including the trench and the stepped shoulder portions. The trench is filled with silicon oxide, and the layer of nitride is etched away with hot phosphoric acid.
A method of forming a trench isolation structure in a silicon substrate, comprising the steps of;
A method of forming a trench isolation structure in a silicon substrate, comprising the steps of:
A method of forming a trench isolation structure in a silicon substrate, comprising the steps of:
A method of forming a trench isolation structure in a silicon substrate, comprising the steps of:
Dependencies are inferred from the claim text.
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Isolation regions comprising dielectric materials: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
Using trench refilling with dielectric materials, e.g. shallow trench isolations: of trenches having shapes other than rectangular or V-shape
Generic packages, interconnections, connectors or other constructional details of devices covered by
Term ended 27 Jul 2021 (estimated)
1. Field of the Invention
The present invention relates to a method of forming a trench isolation structure on a silicon substrate, where the trench is lined with silicon nitride.
2. Description of the Related Art
The present invention will be described in detail further with reference to the following drawings, in which:
FIGS. 1A to 1G are cross-sectional views of a portion of a semiconductor wafer for illustrating conventional steps of fabricating a shallow trench isolation structure on a silicon substrate;
FIGS. 2A to 2H are cross-sectional views of a portion of a semiconductor wafer for illustrating steps of fabricating a shallow trench isolation structure on a silicon substrate according to a first embodiment of the present invention; and
Referring to FIGS. 2A to 2H, there is shown a number of steps for producing a shallow trench isolation structure according to a first embodiment of the present invention. FIG. 2A illustrates a portion of a silicon substrate 21 where a shallow trench will be formed. On the silicon substrate 21 is a pad oxide (silicon dioxide) layer 22 of thickness 5 to 20 nm formed by the conventional thermal oxidation method. The known CVD method is then used to create a pad nitride (silicon nitride) layer 24 of thickness 100 to 300 nm on the pad oxide layer 22. On the pad nitride layer 24 is a patterned resist 26 having an aperture greater than the area in which a trench is to be formed. Anisotropic dry etching method is used to remove portions of the pad oxide layer 22 and pad nitride layer 24 until a portion of the substrate 21 is exposed to the outside through the aperture, forming an aperture 26a. The patterned resist 26 is then stripped and a silicon dioxide layer is deposited over the wafer.
FIG. 2B illustrates the results of an etchback step of anisotropically etching that silicon dioxide layer so that a portion of it remains attached to the sidewall of aperture 26a as a spacer 27, which defines a mask window 27a. This mask window defines the area in which an isolation trench will be formed. If the width of aperture 26a is 200 nm, the spacer 27 has a maximum wall thickness of 100 nm, preferably 30 to 80 nm.
FIG. 2C illustrates the results of an anisotropic dry-etching step of the silicon substrate 21 for anisotropically etching the substrate through the mask window 26a to a depth of 200 to 500 nm to form a trench 28. In this instance, the silicon nitride layer 24 and the silicon dioxide spacer 27 act as a mask. Preferably, the wafer is subjected to a leaning process using diluted hydrofluoric acid, followed by a drying process using the low pressure IPA (isopropyl alcohol) method. These processes eliminate foreign matters and natural oxides which may remain on the surface of the substrate so that no silicon residues remain in the trench after the dry-etching process. Silicon dioxide spacer 27 is then removed using a solution containing hydrofluoric acid to form stepped shoulder portions on the upper edges of the trench 28.