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US 6,551,914 B1Granted
Method of forming polish stop by plasma treatment for interconnection
AssigneeNEC Electronics Corporation
InventorsMieko Suzuki, Akira Kubo
Life of this patent
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Abstract
A semiconductor device in which an interconnection material is buried in a hole formed in an interlevel insulating film arranged on a semiconductor substrate includes a protective layer formed on the surface of the interlevel insulating film that has a lower polishing rate than that of the interconnection material in chemical mechanical polishing. A method of manufacturing this semiconductor device is also disclosed.
Claims10
A method of manufacturing a semiconductor device, comprising the steps of:
- forming a first metal interconnection on a semiconductor substrate by the interposition of a silicon oxide film;
- forming an interlevel insulating film on the semiconductor substrate;
- forming a protective layer with a low polishing rate in chemical mechanical polishing in a surface of said interlevel insulating film by performing, for the surface of said interlevel insulating film, plasma processing using a gas selected from the group consisting of NH3 gas, N2 gas, and a mixture thereof;
- forming a hole through said protective layer and in said interlevel insulating film to reach an upper surface of said first metal interconnection;
- forming a barrier metal film on the surface of said interlevel insulating film including side wall and bottom wall surfaces of the hole;
- forming an interconnection film material on said barrier metal film;
- forming an interconnection by applying chemical mechanical polishing to said interconnection film material and said barrier metal film, in which the polishing is also applied to at least a surface of said protective layer without polishing the surface of said interlevel insulating film, so as to leave interconnection material and barrier metal in only the hole;
- and
- forming a second metal interconnection on the surface of said protective layer.
6 more elements
A method of manufacturing a semiconductor device, comprising the steps of:
- forming a first metal interconnection on a semiconductor substrate by the interposition of a silicon oxide film;
- forming an interlevel insulating film on a semiconductor substrate;
- forming a protective layer comprising a plasma oxide film having a polishing rate ratio of not less than 10 to the interconnection material in chemical mechanical polishing in a surface of said interlevel insulating film;
- forming a hole through said protective layer in said interlevel insulating film to reach an upper surface of said first metal interconnection;
- forming a barrier metal film on the surface of said interlevel insulating film including sidewall and bottom wall surfaces of the hole;
- forming an interconnection film material on said barrier metal film;
- forming an interconnection by chemical mechanical polishing to said interconnection film material and said barrier metal film in which the polishing is also applied to at least a surface of said protective layer without polishing the surface of said interlevel insulating film, so as to leave interconnection material and barrier metal in only the hole;
- and
- forming a second metal interconnection on the surface of said protective layer.
6 more elements
Dependencies are inferred from the claim text.