Methods of fabricating memory cells for nonvolatile memory devices

A method for manufacturing a nonvolatile memory device comprising the following steps:

• (a) providing a semiconductor substrate having a substrate dielectric layer disposed on a surface of the substrate;
• (b) forming a first conductive layer on the substrate dielectric layer;
• (c) forming a second dielectric layer on the first conductive layer;
• (d) patterning the second dielectric layer and the first conductive layer to create at least one polybar having a length extending along a surface of the substrate dielectric layer;
• (e) patterning the at least one polybar substantially perpendicularly to the length of the at least one polybar to thereby parse the at least one polybar into at least one polyisland;
• and
• (f) forming a second conductive layer over the second dielectric layer of the at least one polyisland.

A method for forming polyislands on a substrate for a nonvolatile memory device, the method comprising the following steps:

• (a) providing a substrate having an oxide layer disposed thereupon;
• (b) forming a plurality of bar-like structures on the substrate oxide layer, wherein each bar-like structure extends in a first direction and includes a polysilicon layer and a top layer above the polysilicon layer;
• (c) forming a bottom anti-reflective coating (BARC) layer on the substrate over the plurality of bar-like structures;
• and
• (d) patterning the bar-like structures substantially perpendicularly to the first direction to thereby form a plurality of polyislands, wherein patterning of the bar-like structures comprises performing a first etching process, of which an etching selectivity between the anti-reflective coating layer and the top layer is about 1, and then performing a second etching process, of which an etching selectivity between the top layer and the anti-reflective coating layer is larger than 5, and then performing a third etching process, of which an etching selectivity between the polysilicon layer and the substrate oxide layer is larger than 50.