Method of manufacturing memory device
AssigneePowerchip Semiconductor Corp.
InventorKun-Jung Wu
Life of this patent
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Abstract
A method of manufacturing a memory device. A substrate having an active region, a plurality of gate structures and a plurality of source/drain regions are provided. An inter-layer dielectric layer is formed over the substrate. A global opening that exposes the source/drain regions for forming contacts and the gate structures inside the active region is formed in the inter-layer dielectric layer. A conductive layer that completely fills the global opening is formed over the substrate. A portion of the conductive layer and the inter-layer dielectric layer is removed to expose the upper surface of the gate structures, thereby forming a plurality of contacts between the gate structures.
Claims16
A method of manufacturing a memory device, comprising the steps of:
- providing a substrate having an active region thereon, wherein the active region includes a plurality of gate structures and a plurality of source/drain regions;
- forming a liner layer, for covering the gate structures and the source/drain regions;
- forming an inter-layer dielectric layer over the liner layer, wherein an etching rate of the liner layer is different from that of the inter-layer dielectric layer;
- etching the inter-layer dielectric layer until a portion of the liner layer is exposed to form a global opening in the inter-layer dielectric layer;
- etching the liner layer until the source/drain regions are exposed;
- forming a conductive layer over the substrate that complete fills the global opening;
- and
- removing a portion of the conductive layer and the inter-layer dielectric layer to form contacts that connect electrically with the source/drain regions.
A method of manufacturing dynamic random access memory, comprising the steps of:
- providing a substrate having an active region thereon, wherein the active region further includes a plurality of gate structures and a plurality of source/drain regions;
- forming a liner layer, for covering the gate structures and the source/drain regions;
- forming an inter-layer dielectric layer over the liner layer, wherein an etching rate of the liner layer is different from that of the inter-layer dielectric layer;
- patterning the inter-layer dielectric layer until a portion of the liner layer is exposed to form a global opening;
- etching the liner layer until the source/drain regions are exposed;
- forming a conductive layer over the substrate, wherein the conductive layer completely fills the global opening;
- removing a portion of the conductive layer and the inter-layer dielectric layer to form a first contact and a second contact between the gate structures;
- forming a bit line on the substrate electrically connected to the first contact;
- and
- forming a capacitor on the substrate electrically connected to the second contact.
Dependencies are inferred from the claim text.