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US 6,549,028 B1Granted
Configuration and process for testing a multiplicity of semiconductor chips on a wafer plane
AssigneeInfineon Technologies AG
InventorCarsten Ohlhoff
Life of this patent
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Abstract
Arrangement and method for testing a multiplicity of semiconductor chips at the wafer level The invention relates to an arrangement and a method for testing a multiplicity of semiconductor chips (7) at the wafer level, in which an intermediate wiring plane (10) with a global test bus (12) and test pads (11) is applied to the surface of the wafer (6).
Claims5
A method of testing a multiplicity of semiconductor chips at a wafer level of a semiconductor wafer, which comprises:
- providing a semiconductor wafer having a plurality of semiconductor chips with bonding pads of a given area;
- forming an intermediate wiring plane on the semiconductor wafer with one of a global test bus connected to a plurality of the semiconductor chips and at least one test pad connected to a bonding pad and having an area larger than the given area of the bonding pads;
- forming the intermediate wiring plane of a conductive polymer;
- and
- connecting test signals of a tester device to the semiconductor chips via the intermediate wiring plane.
2 more elements
Dependencies are inferred from the claim text.