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AssigneeHynix Semiconductor Inc.
InventorJae Il Ju
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A semiconductor device includes a semiconductor substrate, a barrier film in a field region of the semiconductor substrate, first and second conductivity-type well regions in the semiconductor substrate and divided by the barrier film in a surface of the semiconductor substrate, a gate insulating film on an entire surface of the semiconductor substrate, a gate electrode on a region of the gate insulating film, a lightly-doped first conductivity-type impurity region formed in the second conductivity-type well region at a first side of the gate electrode, a lightly-doped second conductivity-type impurity region formed in the first conductivity-type well region at a second side of the gate electrode, a conductive pattern connected with the lightly-doped first and second conductivity-type impurity regions and having a constant distance from the gate electrode, an insulating film formed on the semiconductor substrate exposing upper portions of the gate electrode and the conductive pattern, and heavily-doped first and second conductivity-type impurity regions formed on the lightly-doped first and second conductivity-type impurity regions below the conductive pattern.
A semiconductor device, comprising:
A semiconductor device, comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their source or drain regions, e.g. silicided source or drain regions
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their gate sidewall spacers
Inorganic electric semiconductor devices
Term ended 13 Nov 2021 (estimated)
The present invention claims the benefit of Korean Patent Application No. P2000-67429 filed in Korea on Nov. 14, 2000, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device and a method for manufacturing the same that obtains a sub-micron complementary metal-oxide semiconductor (CMOS) device or a high voltage CMOS device.
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principle of the invention. In the drawings:
FIG. 1 is a sectional view of a semiconductor device according to a related art;
FIG. 2 is a sectional view showing an exemplary semiconductor device according to the present invention; and
Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.
FIG. 2 is a cross sectional view showing an exemplary semiconductor device according to the present invention. In FIG. 2, a semiconductor substrate 21 may include a barrier film 22, n-type and p-type well regions 23 and 24, a gate insulating film 25, a gate electrode 28b, lightly-doped p−-type and n−-type impurity regions 33 ad 31, an high temperature and low-pressure dielectric (HLD) film 34, a poly-silicon contact 28a, and heavily-doped p+-type and n+-type impurity regions 37 and 38.
The barrier film 22 may be formed in a field region of the semiconductor substrate. The barrier film 22 may be formed to divide n-type and p-type well regions 23 and 24 in a surface of the semiconductor substrate 21. Then, the gate insulating film 25 may be formed on an entire surface of the semiconductor substrate 21, and the gate electrode 28b may be formed in a region of the gate insulating film 25 having the n-type and p-type well regions 23 and 24. The lightly-doped p−-type and n−-type impurity regions 33 and 31 are formed on the n-type and p-type well regions 23 and 24 at both sides of the gate electrode 28b, respectively. The HLD film 34 may be formed on the semiconductor substrate 21 to have a height equivalent to a height of an upper surface of the gate electrode 28b. Additionally, a polysilicon contact 28a may be formed at a height of the gate electrode 28b to maintain a constant distance from the gate electrode 28b, which may be connected with the lightly-doped p−-type and n−-type impurity regions 33 and 31. Then, the heavily-doped p+-type and n+-type impurity regions 37 and 38 may be formed in the lightly-doped p−-type and n−-type impurity regions 33 and 31 below the polysilicon contact 28a, respectively.