ESD protection clamp with internal zener diode
AssigneeNational Semiconductor Corporation
InventorsDavid Tsuei, Vladislav Vashchenko
Life of this patent
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Abstract
In a ESD protection clamp, breakdown and triggering voltage of the structure are reduced by introducing an internal zener diode structure that has a lower avalanche breakdown than the p-n junction of the ESD device. This introduces extra holes into the source junction region causing electrons to be injected into the junction and into the drain junction region to increase the carrier multiplication rate to increase the current density and lower the triggering voltage and breakdown voltage of devices such as NMOS devices or LVTSCRs.
Claims17
A snap back DGO NMOS ESD protection clamp comprising
- a NMOS structure, and
- at least one internal zener diode structure formed in a ballast region of the NMOS structure, wherein the zener diode has a breakdown voltage that is lower than the breakdown voltage of the drain-p-well junction of the NMOS structure.
A method of reducing the triggering voltage of a NMOS snap back clamp comprising
- forming at least one p-n junction in a ballast region of the NMOS structure to define a zener diode in the NMOS structure, wherein the zener diode has a breakdown voltage that is lower than the breakdown voltage of the drain-p-well junction of the NMOS structure.
A method of reducing the breakdown voltage of an ESD protection device, comprising
- forming at least one zener diode in the ESD device, without contacts, wherein the zener diode has a lower breakdown voltage than that of the ESD device.
An ESD protection device, comprising
- at least one doped region laterally adjacent or within a drain, floating drain or drain ballast region of the ESD protection device, having the opposite polarity to said drain, floating drain or drain ballast region, to form at least one p-n junction having a lower breakdown voltage than the breakdown voltage between said drain, floating drain, or drain ballast, and the substrate or well in which the drain, floating drain, or ballast is formed, wherein said doped region is not provided with a contact.
A method of forming a zener diode structure in a ballast region of a NMOS structure, comprising
- using a blocking mask to define an undoped region during formation of the ballast region, and
- doping the undoped region with opposite polarity to the ballast region, during formation of other regions of said opposite polarity.
Dependencies are inferred from the claim text.