Memory cell, memory cell arrangement and fabrication method
AssigneeInfineon Technologies AG
InventorsHerbert Palm, Josef Willer
Life of this patent
Estimating the term…
Abstract
An electrically conductive layer or layer sequence preferably includes a metal-containing layer applied to a metal silicide or a polysilicon layer to reduce the resistance of buried bit lines. The layer or layer sequence has been patterned in strip form so as to correspond to the bit lines and is arranged on the source/drain regions of memory transistors having an ONO memory layer sequence and gate electrodes that are arranged in trenches. The metal silicide is preferably cobalt silicide, and the metal-containing layer is preferably tungsten silicide or WN/W.
Claims10
A memory cell, comprising:
- a semiconductor body having semiconductor material and a top side;
- a memory transistor having a gate electrode configured on said top side of said semiconductor body, said memory transistor having a source region and a drain region that are formed in said semiconductor material;
- a trench that is formed in said semiconductor body between said source region and said drain region, said gate electrode being configured in said trench;
- a layer sequence including boundary layers and a memory layer located between said boundary layers, said layer sequence being configured at least between said source region and said gate electrode and at least between said drain region and said gate electrode;
- a portion of a bit line formed by an electrically conductive layer patterned in a strip on said source region;
- and
- a portion of a bit line formed by an electrically conductive layer patterned in a strip on said drain region.
A configuration, comprising:
- a plurality of memory cells;
- each one of said plurality of said memory cells including:
- a semiconductor body having semiconductor material and a top side;
- a memory transistor having a gate electrode configured on said top side of said semiconductor body, said memory transistor having a source region and a drain region that are formed in said semiconductor material;
- a trench that is formed in said semiconductor body between said source region and said drain region, said gate electrode being configured in said trench;
- a layer sequence including boundary layers and a memory layer located between said boundary layers, said layer sequence being configured at least between said source region and said gate electrode and at least between said drain region and said gate electrode;
- a portion of a bit line formed by an electrically conductive layer patterned in a strip on said source region;
- and
- a portion of a bit line formed by an electrically conductive layer patterned in a strip on said drain region;
- and
- a plurality of word lines selected from the group consisting of metal-containing layers and layer sequences;
- said gate electrode of each one of said plurality of said memory cells being connected to one of said plurality of said word lines;
- said source region of one of said plurality of said memory cells serving as said drain region of an adjacent one of said plurality of said memory cells;
- and
- said drain region of said one of said plurality of said memory cells serving as said source region of another adjacent one of said plurality of said memory cells.
Dependencies are inferred from the claim text.