Low resistance contact structure for a select transistor of EEPROM memory cells in a NO-DPCC process

A semiconductor memory device, comprising:

• a row of memory cells, each memory cell comprising an information storing element and a related select transistor for selecting the storing element, said select transistor comprising a gate oxide region over a silicon substrate, a lower polysilicon layer and an upper polysilicon layer superimposed to said gate oxide region and electrically insulated therebetween by an intermediate dielectric layer interposed between them, the gate oxide regions of the select transistors of said row being separated by field oxide regions, said lower and upper polysilicon layers and said intermediate dielectric layer extending along said row over the gate oxide regions of the select transistors and over the field oxide regions, wherein along said row is an opening in said upper polysilicon layer, intermediate dielectric layer, and lower polysilicon layer, inside of which a first contact element suitable to electrically connect said lower and upper polysilicon layers is inserted, wherein the row further comprises an upper insulating layer positioned on the upper polysilicon layer, an upper conductive layer positioned on the upper insulating layer, and a second contact element that extends through the upper insulating layer to connect the upper conductive layer with the upper polysilicon layer, wherein the upper insulating layer insulates the first contact element from direct contact with the upper conductive layer.