Semiconductor memory device with increased level of integration

A semiconductor memory device on a semiconductor substrate having a memory cell array area and a peripheral circuit area, comprising:

• landing pads formed of a conductive material contacting source and drain regions of an access transistor in the memory cell array area;
• a first resistor device on the semiconductor substrate in the peripheral circuit area formed of a same material as the landing pads;
• a first interlayer insulation layer having openings to expose the landing pads formed on the overall surface of the semiconductor substrate having the landing pads and the first resistor device;
• a bit line contacting the landing pad that is in contact with the drain region of the access transistor, the bit line having an opening to expose the landing pad that is in contact with the source region of the access transistor, and formed on the first interlayer insulation layer in the memory cell array area;
• a second interlayer insulation layer having an opening to expose the landing pad that is in contact with the source region of the access transistor formed on the bit line and first interlayer insulation layer;
• a storage electrode as a lower electrode of a capacitor contacting the landing pad that is in contact with the source region of the access transistor and a part of the second interlayer insulation layer surrounding the opening therein;
• a dielectric layer on the storage electrode;
• a plate electrode as an upper electrode of the capacitor on said dielectric layer in the memory cell array area, including exposed portions of the second interlayer insulation layer in the memory cell array area;
• a second resistor device on a part of the second interlayer insulation layer in the peripheral circuit area formed of a same material as the plate electrode;
• and
• a third interlayer insulation layer on the overall surface of the semiconductor substrate having the capacitor, access transistor, bit line, and first and second resistor devices.