Method for forming integrated circuit having MONOS device and mixed-signal circuit
AssigneeMacronix International Co., Ltd.
InventorsErh-Kun Lai, Hsin-Huei Chen, Ying-Tso Chen, Shou-Wei Hwang, Yu-Ping Huang
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Abstract
A method for forming an integrated circuit having metal-oxide nitride-oxide semiconductor (MONOS) memories and mixed-signal circuits is disclosed. The invention integrates non-volatile memory devices such as MONOS devices and logic devices such as MOS devices as well as PIP capacitors into SOC devices with reduced process steps.
Claims20
A method for forming an integrated circuit having metal-oxide nitride-oxide semiconductor memories and mixed-signal circuits, said method comprising:
- providing a substrate having an array region having a first dielectric layer, a second dielectric layer and a third dielectric layer stacked in sequence and a periphery region having said first dielectric layer thereon;
- forming a first conductive layer over said array region and said periphery region;
- forming a photoresist layer over said array region;
- implanting dopant ions into said first conductive layer;
- removing said photoresist layer;
- patterning to etch said first conductive layer to form a second conductive layer and a third conductive layer on said periphery region;
- removing said third dielectric layer to expose said second dielectric layer;
- removing said exposed first dielectric layer on said periphery region to expose said substrate;
- oxidizing said second dielectric layer, said substrate, said second conductive layer and said third conductive layer to form a fourth dielectric layer therein;
- forming a fourth conductive layer over said fourth dielectric layer;
- and
- patterning to etch said fourth conductive layer to form a fifth conductive layer on said array region and a sixth conductive layer on said fourth dielectric layer and said third conductive layer.
A method for forming an integrated circuit having metal-oxide nitride-oxide semiconductor memories and mixed-signal circuits, said method comprising:
- providing a substrate having an array region having a first silicon dioxide layer, a silicon nitride layer and a second silicon dioxide layer stacked in sequence and a periphery region having said first silicon dioxide layer thereon;
- forming a first conductive layer over said array region and said periphery region;
- forming a photoresist layer over said array region;
- implanting dopant ions into said first conductive layer;
- removing said photoresist layer;
- patterning to etch said first conductive layer to form a second conductive layer and a third conductive layer on said periphery region;
- removing said second silicon dioxide layer to expose said silicon nitride layer;
- removing said exposed first silicon dioxide layer on said periphery region to expose said substrate;
- oxidizing said silicon nitride layer, said substrate, said second conductive layer and said third conductive layer to form a third silicon dioxide layer therein;
- forming a fourth conductive layer over said third silicon dioxide layer;
- and
- patterning to etch said fourth conductive layer to form a fifth conductive layer on said array region and a sixth conductive layer on said third silicon dioxide layer and said third conductive layer.
A method for forming an integrated circuit having metal-oxide nitride-oxide semiconductor memories and mixed-signal circuits, said method comprising:
- providing a substrate having an array region having a first silicon dioxide layer, a silicon nitride layer and a second silicon dioxide layer stacked in sequence and a periphery region having said first silicon dioxide layer thereon;
- forming a first conductive layer over said array region and said periphery region;
- forming a photoresist layer over said array region;
- implanting dopant ions into said first conductive layer;
- removing said photoresist layer;
- patterning to etch said first conductive layer to form a second conductive layer and a third conductive layer on said periphery region;
- removing said second silicon dioxide layer to expose said silicon nitride layer;
- removing said exposed first silicon dioxide layer on said periphery region to expose said substrate;
- oxidizing said silicon nitride layer, said substrate, said second conductive layer and said third conductive layer to form a third silicon dioxide layer therein by an in situ steam generated oxidation process;
- forming a fourth conductive layer over said third silicon dioxide layer;
- and
- patterning to etch said fourth conductive layer to form a fifth conductive layer on said array region and a sixth conductive layer on said third silicon dioxide layer and said third conductive layer.
Dependencies are inferred from the claim text.