Semiconductor processing methods, and semiconductor constructions
AssigneeMicron Technology, Inc.
InventorJigish D. Trivedi
Life of this patent
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Abstract
The invention includes a dual-damascene semiconductor processing method. A semiconductor substrate is provided, and the substrate includes a conductive structure and an insulative layer over the conductive structure. A via is etched through the insulative layer and into the conductive structure, and a resist is formed within the via. A material is formed over the resist and substrate. A portion of the material in contact with the resist is hardened, and another portion of the material that does not contact the resist is not hardened. The portion of the material which is not hardened is removed, and a slot is etched into the insulative layer.
Claims46
A semiconductor processing method, comprising:
- forming a first opening extending into a substrate and having a periphery at least partially defined by the substrate;
- forming a mass within the first opening to only partially fill the first opening, the mass comprising a resist;
- forming a material over the mass and within the partially-filled opening;
- releasing at least one substance from the mass which forms chemical cross-links within the material;
- after forming the cross-links within the material, removing at least some of the periphery of the first opening to form a second opening;
- and
- after forming the second opening, removing the mass and cross-linked material from within the first opening.
A semiconductor processing method, comprising:
- forming a first opening extending into a substrate and having a periphery at least partially defined by the substrate;
- forming a mass with in the first opening to only partially fill the first opening;
- forming a material over the mass and within the partially-filled opening;
- releasing at least one substance from the mass which forms chemical cross-links within the material;
- after forming the cross-links within the material, removing at least some of the periphery of the first opening to form a second opening;
- after forming the second opening, removing the mass and cross-linked material from within the first opening;
- wherein:
- the substrate comprises a monocrystalline silicon wafer having a conductive structure thereover, and further comprises an insulative layer over the conductive structure;
- the first opening is formed to extend through the insulative layer and to the conductive structure;
- and
- the mass is formed physically against the conductive structure.
A dual damascene semiconductor processing method, comprising:
- providing a semiconductor substrate which includes a conductive structure and an insulative layer over the conductive structure;
- etching a via through the insulative layer and to proximate the conductive structure;
- forming an organic composition within the via;
- applying a material over the organic composition and substrate, a portion of the material being in contact with the organic composition and another portion not being in contact with the organic composition;
- selectively altering chemical properties of the portion of the material in contact with the organic composition while not altering the chemical properties of at least some of the portion of the material that does not contact the organic composition;
- removing the portion of the material that does not have the altered chemical properties;
- and
- etching a slot into the insulative layer and overlapping the via;
- the organic composition and portion of the material contacting the organic composition protecting the conductive structure during the etching of the slot.
A semiconductor processing method, comprising:
- forming a first opening extending into a substrate, the opening having a bottom surface;
- forming photoresist within the first opening to at least partially cover the bottom surface of the first opening;
- forming a material over the photoresist;
- releasing at least one substance from the photoresist which forms chemical cross-links within the material;
- after forming cross-links within the material, forming a second opening which overlaps at least a portion of the first opening;
- and
- after forming the second opening, removing the photoresist and cross-linked material from within the first opening.
A semiconductor processing method, comprising:
- providing a semiconductor substrate comprising a conductive mass and an insulative mass over the conductive mass;
- forming a first opening extending into the substrate and to the conductive mass;
- forming photoresist within the first opening to cover the conductive mass;
- forming a material over the photoresist;
- releasing at least one substance from the photoresist which forms chemical cross-links within the material;
- after forming the cross-links within the material, forming a second opening which overlaps at least a portion of the first opening;
- after forming the second opening, removing the photoresist and cross-linked material from within the first opening;
- and
- after removing the photoresist and cross-linked material, forming a conductive interconnect within the first and second openings, the conductive interconnect being in electrical contact with the conductive mass.
A semiconductor processing method, comprising:
- providing a semiconductor substrate comprising a conductive mass and an insulative mass over the conductive mass;
- forming a first opening extending into the substrate and to the conductive mass;
- forming a first organic material within the first opening to cover the conductive mass;
- forming a second organic material over the first organic material, the second organic material being more resistive to selected etching conditions than the first organic material;
- utilizing the selected etching conditions to form a second opening which overlaps at least a portion of the first opening;
- after forming the second opening, removing the first and second organic materials from within the first opening;
- and
- after removing the first and second organic materials, forming a conductive interconnect within the first and second openings, the conductive interconnect being in electrical contact with the conductive mass.
Dependencies are inferred from the claim text.