Method of fabricating interlevel connectors using only one photomask step

A method for fabricating integrated circuit interconnects comprising metal-filled vias and trenches, comprising the steps of:

• forming first horizontal metal interconnector lines on an insulated semiconductor substrate;
• forming a stack of horizontal insulating layers, alternating between first, second, third, and fourth etch stop layers and first, second and third dielectric layers, the fourth stop layer being the top layer;
• depositing a first photoresist layer over said fourth stop layer;
• patterning said photoresist so that at least one resist structure remains, surrounding each desired via location, while elsewhere said fourth stop layer is exposed;
• said remaining photoresist structure having an outside geometry defining the desired outline of each of said trenches and further providing a centered vertical hole defining the desired outline of each of said vias, wherein the area surrounding said photoresist structure is wide open relative to the geometry of said hole;
• selectively and differentially etching into said fourth stop layer for a period of time sufficient to remove all of the fourth stop layer in said open area outside said photoresist structure, thereby exposing said third dielectric layer, while only partially removing said fourth stop layer, during the same period of time, inside said photoresist structure, thereby defining said desired via outline in said fourth stop layer;
• selectively removing said exposed third dielectric layer, thereby exposing said third stop layer;
• stripping said photoresist structure;
• forming a second photoresist layer over said exposed third stop layer, thereby defining said desired trench outline in said second photoresist layer;
• selectively etching said photoresist layer to expose the remaining portion of said fourth stop layer, with partially etched via inside;
• deepening said partially etched via by selectively etching it completely through said fourth stop layer and completely through said third dielectric layer;
• selectively etching said partially etched via through said third stop layer, thereby defining a via in said third stop layer, while concurrently removing the remainder of said fourth stop layer;
• selectively etching said via in said third stop layer through said second dielectric layer, thereby defining a via in said second dielectric layer, while concurrently removing the remainder of said third dielectric layer, thereby opening a desired trench outline in said second photoresist layer;
• selectively continuing to deepen said via in said second dielectric layer through said second stop layer and then said first dielectric layer, while concurrently etching said trench through said third stop layer and said second dielectric layer;
• selectively etching said via in said first stop layer through said first stop layer, thereby exposing said first metal interconnector lines, while concurrently etching said trench partially through said second stop layer;
• and
• depositing a second horizontal metal interconnector layer on the remainder of said second stop layer while concurrently filling said via and trench with metal, thereby creating a vertical interconnect between said second and first horizontal metal layers.