Twin well methods of forming CMOS integrated circuitry

A twin-well method of forming CMOS integrated circuitry having first and second conductivity type transistor gates comprising:

• depositing a transistor gate layer of a semiconductor material over a semiconductor substrate;
• after depositing the transistor gate layer and in one masking step, effectively masking a first substrate area configured for formation of first conductivity type transistors while leaving a second substrate area configured for formation of second conductivity type transistors effectively unmasked;
• conducting a first conductivity type well implant into the second substrate area and a second conductivity type gate implant into the transistor gate layer within the second substrate area in the one masking step;
• in another masking step after the one masking step, effectively masking the second substrate area and only a portion of the first substrate area with a masking material while leaving a majority of the first substrate area effectively unmasked;
• with the masking material in place, conducting a first conductivity type implant into the transistor gate layer within the first substrate area and leaving a substantially undoped region of transistor gate layer semiconductor material within the first substrate area;
• after conducting the first conductivity type implant into the transistor gate layer within the first substrate area, laterally etching away at least some of the masking material within the first substrate area;
• and
• after laterally etching away the masking material within the first substrate area, conducting a second conductivity type well implant within the first substrate area.

A twin-well method of forming CMOS integrated circuitry having first and second conductivity type transistor gates comprising:

• depositing a transistor gate layer of a semiconductor material over a semiconductor substrate;
• forming a first conductivity type well region and second conductivity type doped semiconductor material of the gate layer within a second substrate area configured for formation of second conductivity type transistors;
• effectively masking the second substrate area and only a portion of a first substrate area configured for formation of first conductivity type transistors with a masking material while leaving a majority of the first substrate area effectively unmasked;
• with the masking material in place, conducting a first conductivity type implant into the transistor gate layer within the first substrate area and leaving a substantially undoped region of transistor gate layer semiconductor material within the first substrate area;
• after conducting the first conductivity type implant into the transistor gate layer within the first substrate area, laterally etching away at least some of the masking material within the first substrate area;
• and
• after laterally etching away the masking material within the first substrate area, conducting a second conductivity type well implant within the first substrate area.

A method of forming CMOS integrated circuitry having first and second conductivity type transistor gates comprising:

• depositing a transistor gate layer of a semiconductor material over a semiconductor substrate;
• doping the transistor gate layer semiconductor material with a second conductivity type impurity within a second substrate area configured for formation of second conductivity type transistors;
• effectively masking the second substrate area and only a portion of a first substrate area configured for formation of first conductivity type transistors with a masking material while leaving a majority of the first substrate area effectively unmasked;
• and
• with the masking material in place, conducting a first conductivity type implant into the transistor gate layer within the first substrate area and leaving a substantially undoped region of transistor gate layer semiconductor material within the first substrate area;
• and
• after conducting the first conductivity type implant into the transistor gate layer within the first substrate area, removing the masking material from the substrate and leaving substantially undoped semiconductor material of the transistor gate layer intermediate a first conductivity type doped region and a second conductivity type doped region of the transistor gate layer.

A twin-well method of forming CMOS integrated circuitry having first and second conductivity type transistor gates comprising:

• providing a semiconductor substrate having isolation regions formed therein;
• forming a transistor gate dielectric layer over the semiconductor substrate;
• depositing a transistor gate layer of a semiconductor material over the transistor gate dielectric layer;
• after depositing the transistor gate layer and in one masking step, masking a first substrate area for formation of first conductivity type transistors with a first masking material while leaving a second substrate area for formation of second conductivity type transistors unmasked;
• conducting a first conductivity type well implant into the second substrate area and a second conductivity type gate implant into the transistor gate layer within the second substrate area in the one masking step;
• removing the first masking material from the first substrate area and masking the second substrate area with another masking material;
• while the second substrate area is masked with a second masking material, conducting a first conductivity type gate implant into the transistor gate layer within the first substrate area and a second conductivity type well implant into the first substrate area;
• removing the second masking material from the second substrate area and forming transistor gates over the first and second substrate areas from the transistor gate layer;
• and
• forming source/drain regions proximate the transistor gates in the first and second substrate areas.

A twin-well method of forming CMOS integrated circuitry having first and second conductivity type transistor gates comprising:

• providing a semiconductor substrate having isolation regions formed therein;
• forming a transistor gate dielectric layer over the semiconductor substrate;
• depositing a transistor gate layer of a semiconductor material over the transistor gate dielectric layer;
• after depositing the transistor gate layer and in one masking step, masking a first substrate area for formation of first conductivity type transistors with a first masking material while leaving a second substrate area for formation of second conductivity type transistors effectively unmasked;
• conducting a first conductivity type well implant into the second substrate area and a second conductivity type gate implant into the transistor gate layer within the second substrate area in the one masking step;
• removing the first masking material from the first substrate area and in another masking step after the one masking step, masking the second substrate area and only a portion of the first substrate area proximate the second substrate area with a second masking material while leaving a majority of the first substrate area effectively unmasked;
• with the second masking material in place, conducting a first conductivity type gate implant into the transistor gate layer within the first substrate area and leaving a substantially undoped region of transistor gate layer semiconductor material within the first substrate area proximate the second conductivity type gate implant into the transistor gate layer;
• after conducting the first conductivity type gate implant into the transistor gate layer within the first substrate area, isotropic etching away at least some of the second masking material to remove it from being received within the first substrate area while leaving the second substrate area effectively covered;
• after the isotropic etching, conducting a second conductivity type well implant within the first substrate area;
• removing the second masking material from within the second substrate area and forming transistor gates over the first and second substrate areas from the transistor gate layer;
• and
• forming source/drain regions proximate the transistor gates in the first and second substrate areas.

A twin-well method of forming CMOS integrated circuitry having first and second conductivity type transistor gates comprising:

• providing a semiconductor substrate having first and second regions;
• depositing a transistor gate layer over the semiconductor substrate;
• conducting a first conductivity type well implant and a second conductivity type gate implant in a first common masking step, wherein the first region is effectively masked;
• conducting a second conductivity type well implant and a first conductivity type gate implant in a second common masking step, wherein the second region is effectively masked;
• and
• after the first and second common masking steps, forming first and second conductivity type transistor gates comprising at least a portion of the transistor gate layer.