Method of making nonvolatile memory device having reduced capacitance between floating gate and substrate

A method of making a nonvolatile memory device, comprising the steps of:

• sequentially forming a tunnel dielectric layer and a conductive layer over a substrate;
• patterning the conductive layer, the tunnel dielectric layer, and the substrate to form trenches in the substrate;
• filling the trenches with shallow trench isolation (STI) structures that protrude over the substrate;
• recessing the conductive layer below a top surface of the STI structures to leave a recess;
• forming a spacer on sidewalls of the recess, the spacer covering a portion of the conductive layer to serve as an oxidation mask;
• growing a thermal oxide layer on the conductive layer where it is not covered by the spacer;
• removing the spacer to expose the conductive layer;
• etching an opening through the conductive layer using the thermal oxide layer as an etch mask to define a floating gate;
• removing the oxide layer;
• forming an inter-gate dielectric layer conformally lining the opening and the floating gate;
• and
• forming a control gate layer over the inter-gate dielectric layer and filling the opening.

A method of making a nonvolatile memory device, comprising the steps of:

• forming a mask layer on a semiconductor substrate;
• patterning the mask layer and the substrate to form trenches in the substrate;
• filling the trenches with shallow trench isolation (STI) structures that protrude over the substrate;
• removing the mask layer to leave a cavity between the STI structures;
• forming a tunnel dielectric layer on the substrate;
• forming a conductive layer on the tunnel dielectric layer and filling the cavity;
• recessing the conductive layer below a top surface of the STI structures to leave a recess;
• forming a spacer on sidewalls of the recess, the spacer covering a portion of the conductive layer to serve as an oxidation mask;
• growing a thermal oxide layer on the conductive layer where it is not covered by the spacer;
• removing the spacer to expose the conductive layer;
• etching an opening through the conductive layer using the thermal oxide layer as an etch mask to define a floating gate;
• removing the oxide layer;
• forming an inter-gate dielectric layer conformally lining the opening and the floating gate;
• and
• forming a control gate layer over the inter-gate dielectric layer and filling the opening.