Spacer formation process using oxide shield
AssigneesInfineon Technologies AG, International Business Machines Corporation
InventorsJochen Beintner, Stephan Kudelka, Thomas Dyer
Life of this patent
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Abstract
In the formation of a semiconductor structure, where spacer formation is strongly dependent on the structure (e.g. taper), the improvement of a spacer formation on a poly stud planarized to pad nitride where an oxide is formed on top of the poly prior to the pad nitride strip, so that after pad nitride removal, the poly is etched back and nitride is deposited conformal followed by anisotropic nitride RIE etch, so that the oxide protects the nitride underneath from being etched.
Claims21
In a method for formation of spacers during preparation of semiconductor integrated circuit devices, the improvement of forming an oxide on top of a poly prior to a nitride strip, on a poly stud planarized to a pad nitride, comprising:
- a) subjecting a semiconductor structure comprising a pad nitride and pad oxide underneath said pad nitride to poly oxidation selective to said pad nitride;
- b) forming a vertical gate cap nitride by deposition;
- c) forming a shallow trench isolation (STI);
- d) depositing a support cover oxide in a support area;
- e) performing a pad nitride strip in an array area;
- f) performing an isotropic poly etch back;
- g) performing a spacer sidewall nitride deposition and spacer etch selective to oxide;
- h) performing an array top oxide (ATO) by deposition and oxide planarization;
- i) performing an array cap nitride and cap oxide deposition, and structuring said cap oxide;
- j) forming a cap nitride and pad nitride strip in the support area processing comprising:
- I) performing a pad oxide strip of oxide underneath said pad nitride;
- II) performing oxidation of a screen oxide;
- III) performing support well implants by masking;
- IV) performing a screen oxide strip;
- V) performing gate oxidation;
- and
- VI) forming a poly #1 deposition
- k) structuring the poly #1 deposition;
- l) performing an array cap oxide etch, an array cap nitride etch and an oxide etch to expose a vertical gate poly;
- m) performing either a gate conductor poly #2 deposition or a combination of a gate conductor poly #2 deposition and WSi or W/WN deposition followed by a cap nitride deposition;
- n) structuring the gate conductor;
- and
- o)
- I) performing gate conductor sidewall oxidation;
- II) forming a gate conductor sidewall spacer;
- III) performing source/drain implants by masking;
- p) performing a inter layer dielectric (ILD)oxide deposition;
- planarization of the ILD oxide and stopping on the cap nitride;
- contact structuring;
- and affecting contact fill adjacent the gate conductor sidewall spacer.
Dependencies are inferred from the claim text.