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US 6,545,297 B1Granted
High density vertical SRAM cell using bipolar latchup induced by gated diode breakdown
AssigneeMicron Technology, Inc.
InventorsWendell P. Noble, Jr., Leonard Forbes
Life of this patent
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Abstract
Area efficient static memory cells and arrays containing p-n-p-n transistors which can be latched in a bistable on state. Each transistor memory cell includes a gate which is pulse biased during the write operation to latch the cell. Also provided is a CMOS fabrication process to create the cells and arrays.
Claims27
A memory cell, comprising:
- a gated diode structure having bistable current states for storing information, one of said current states being achieved by operation of gate-induced latchup of said diode structure;
- and
- a gate structure, said gate structure gating said diode structure,
- wherein said diode structure is isolated by trenches, and said gate structure is adjacent to said diode structure and at least partially within one of said trenches, and wherein said memory cell has an area of about 4 F2 where F is the minimum lithographic dimension.
1 more element
A circuit for storing information as one of at least two possible bistable current states, comprising:
- at least one vertically stacked p-n-p-n structure comprising complementary transistors including a p-n-p transistor and a n-p-n transistor;
- and
- a single transistor gate shared by the p-n-p transistor and the n-p-n transistor and spanning the central n-p junction of said p-n-p-n structure
- wherein said circuit is a static random access memory cell having an area of about 4 F2 where F is the minimum lithographic dimension.
1 more element
A SRAM array, comprising
- a substrate;
- a plurality of vertical p-n-p-n transistors;
- a first set of isolation trenches between said p-n-p-n transistors for isolating said transistors in a first direction;
- a second set of isolation trenches orthogonal to said first set of trenches for isolating said transistors in a second direction;
- gate lines in one of said first or second sets of trenches and connecting the central p-n junctions of at least some of said plurality of transistors;
- and
- an insulating material layer between each of said p-n-p-n transistors and the substrate, horizontally isolating the transistors.
4 more elements
A computer system, comprising:
- a processor;
- and
- a memory circuit connected to the processor, the memory circuit containing at least one memory cell comprising a gated p-n-p-n diode having bistable current states for storing information, one of said current states being achieved by operation of gate-induced latch-up of said p-n-p-n diode, wherein said memory cell has an area of about 4 F2 where F is the minimum lithographic dimension.
A method of storing a binary logic value comprising:
- inducing latch-up in a gated diode, wherein the act of inducing latch-up comprises application of a pulsed gate bias and inducement of carrier multiplication and breakdown in the gated diode.
Dependencies are inferred from the claim text.