Latch chain having improved sensitivity

Abstract

A latch chain having improved input voltage sensitivity. The chain includes a first latch, an amplifier, and a second latch connected in series. The second latch is a conventional latch. The first latch is modified to have a higher sensitivity and lower output voltage swing than conventional latches. The modified latch includes a pair of matched output transistors that generate output voltages and a pair of matched biasing circuits to bias the bases of the output transistors with bias voltages. A sample stage is connected so as to apply first biasing currents to one of the biasing circuits in response to input voltages applied to the first latch during the sample period. In addition, a hold stage is connected so as to apply second biasing currents to the biasing circuits during a hold period. The sample and hold stages are configured to apply different voltage differences between the bases of the output transistors.

Dependencies are inferred from the claim text.