Digital configurable macro architecture

A programmable digital device comprising:

• an array of programmable digital circuit blocks, each programmable digital circuit block is selectably configurable to perform any one of a plurality of predetermined digital functions, wherein each programmable digital circuit block is dynamically configurable from any one of said predetermined digital functions to any one of said predetermined digital functions, wherein each programmable digital circuit block includes:
• a configuration register for receiving and storing a plurality of configuration data corresponding to any one of said plurality of predetermined digital functions, wherein said configuration register configures said programmable digital circuit block to perform any one of said plurality of predetermined digital functions based on said configuration data;
• and
• a plurality of selectable logic circuits which are dependent on said plurality of predetermined digital functions such that to minimize size of said programmable digital circuit block, wherein said configuration register configures and selects any of said plurality of said selectable logic circuits to perform one of said plurality of predetermined digital functions based on said configuration data.

A controller apparatus comprising:

• a first programmable digital circuit block which is selectably configurable to perform any one of a plurality of predetermined digital functions, wherein said first programmable digital circuit block is dynamically configurable from any one of said predetermined digital functions to any one of said predetermined digital functions, wherein said first programmable digital circuit block includes:
• a first configuration register for receiving and storing a plurality of configuration data corresponding to any one of said plurality of predetermined digital functions, wherein said first configuration register configures said first programmable digital circuit block to perform any one of said plurality of predetermined digital functions based on said configuration data;
• and
• a first plurality of selectable logic circuits which are dependent on said plurality of predetermined digital functions such that to minimize size of said first programmable digital circuit block, wherein said first configuration register configures and selects any of said first plurality of said selectable logic circuits to perform one of said plurality of predetermined digital functions based on said configuration data.