Semiconductor integrated circuit

#The present invention generally relates to semiconductor integrated circuits, and more particularly to a semiconductor integrated circuit having a scan path circuit which uses a scan-in/out system.

#Semiconductor technology has developed considerably over the recent years, and the integration density of semiconductor integrated circuits such as large scale integrated circuits (LSIs) and very large scale integrated circuits (VLSIs) has improved. Due to the increase in the integration density of the semiconductor integrated circuits, the number of terminals for data input/output has increased, and the number of input/output cells for data input/output has also increased. For this reason, it is impossible to secure the required number of input/output cells by the method of arranging the input/output cells only in a peripheral part of a chip of the semiconductor integrated circuit, and the input/output cells are now being arranged on the entire surface of the chip of the semiconductor integrated circuit. However, when the input/output cells are arranged on the entire surface of the chip, it is difficult to carry out a test which uses a prober.

#On the other hand, as the integration density of the semiconductor integrated circuit increases, it becomes more and more difficult to make a diagnosis regarding whether or not the semiconductor integrated circuit operates as originally designed. As a result, there is a problem in that the cost involved in testing the semiconductor integrated circuit increases. Accordingly, there are demands to realize a semiconductor integrated circuit which can facilitate the test and reduce the cost involved in testing the semiconductor integrated circuit.

#FIG. 1 is a diagram showing an LSI chip in a plan view for explaining an example of a conventional wafer probing test;

#FIG. 2 is a diagram showing an LSI chip in a plan view for explaining another example of the conventional wafer probing test;

#FIG. 3 is a plan view for explaining a first embodiment of a semiconductor integrated circuit according to the present invention;

#A description will be given of a first embodiment of a semiconductor integrated circuit according to the present invention, by referring to FIGS. 3 through 6. In this embodiment, the present invention is applied to an LSI chip.

#FIG. 3 shows an LSI chip 1 having input/output cells 2 arranged on the surface of the LSI chip 1. Each input/output cell 2 is provided with a pad 3. The input/output cells 2 for scan-in/out are arranged in the outer peripheral end region of the LSI chip 1, that is, in the peripheral part of the LSI chip 1. The pad 3 of the input cell 2 for scan-in is denoted by SI, while the pad 3 of the output cell for scan-out is denoted by SO. On the other hand, the input/output cells 2 for data input/output are arranged over the entire surface of the LSI chip 1. A boundary scan chain which is indicated by a bold line in FIG. 3 or an internal (logic) scan chain which is indicated by a dotted line in FIG. 3 is connected to each input/output cell 2 for scan-in/out as a scan path circuit. Of course, FIG. 3 only shows a part of the input/output cells 2 for scan-in/out.

#The boundary scan which is one method of testing the LSI is originally intended to also confirm whether or not signal transfers are normally carried out between the LSIs. But in this embodiment, the boundary scan chain is used as a means of setting inputs to or reading outputs from those input/output cells 2 which cannot be contacted by the prober needles. In other words, the inputs to or the outputs from those input/output cells 2 which cannot be contacted by the prober needles are set or read out via the boundary scan chain.