Structure for reduction of base and emitter resistance and related method

Abstract

According to one embodiment, a semiconductor device including a base, an emitter, and an emitter contact on top of the emitter is disclosed. For example, the semiconductor device can be a silicon-germanium heterojunction bipolar transistor, in which the base is formed from epitaxially deposited silicon-germanium, the emitter is formed from polycrystalline silicon, and the emitter contact is formed as a borderless contact on top of the emitter. The base includes a link base region, an extrinsic base region, and an intrinsic base region. For example, the intrinsic base region can be the region of the base in which the base-emitter junction is formed by out-diffusion of dopants from the emitter. The extrinsic base can be a low resistance region formed by implantation doping to provide a low resistance electrical path from a base contact to the intrinsic base region through the extrinsic base and link base regions. A disclosed structure also includes a link spacer. For example, the link spacer can be composed of silicon nitride. The link spacer can be formed by conformal deposition of dielectric material over the emitter followed by an etch back. The link spacer determines the length of the link base region situated directly below the link spacer and between the intrinsic and extrinsic base regions. The link spacer dielectric also provides electrical isolation for the base and emitter, allowing the use of a low resistance borderless emitter contact directly on top of the emitter.

Dependencies are inferred from the claim text.