Vertical fuse structure for integrated circuits containing an exposure window in the layer over the fuse structure to facilitate programming thereafter

An integrated circuit structure capable of being programmed comprising:

• a substrate;
• and
• a plurality of disconnectable fuses formed over the substrate and adjacent to one another, each of the plurality of disconnectable fuses including:
• a first interconnect layer disposed above the substrate;
• a first insulator layer disposed above the first interconnect layer;
• a second interconnect layer disposed above the second insulator layer;
• a via disposed in the second insulator layer electrically connecting the first interconnect layer to the second interconnect layer, and
• another insulating layer disposed on and over the second interconnect layer, the another insulating layer including an exposure window aligned with and having a top surface area larger than a top surface area of the via disposed below, wherein the another insulating layer is completely removed within the exposure window to facilitate the subsequent programming of the integrated circuit structure by etching of the second interconnect layer and at least a portion of the via at the exposure window of the fuse to be etched.

An integrated circuit structure capable of being programmed comprising:

• a substrate;
• and
• a plurality of disconnectable fuses formed over the substrate and adjacent to one another, such that the plurality of disconnectable fuses includes all of the disconnectable fuses on the substrate, each of the plurality of disconnectable fuses including:
• a first interconnect layer disposed above the substrate;
• a first insulator layer disposed above the first interconnect layer;
• a second interconnect layer disposed above the second insulator layer;
• a via disposed in the second insulator layer electrically connecting the first interconnect layer to the second interconnect layer, and
• another layer disposed on and over the second interconnect layer, the another layer including a exposure window aligned with and having a top surface area larger than a top surface area of the via disposed below that facilitates the subsequent programming of the integrated circuit structure by etching of the second interconnect layer and at least a portion of the via at the exposure window of the fuse to be etched.