Semiconductor device having shallow trench isolation structure and manufacturing method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorJoo-Wook Park
Life of this patent
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Abstract
A semiconductor device having a shallow trench isolation (STI) structure, which is capable of reducing leakage current in a P-FET and improving the device characteristics of a memory device, and a manufacturing method thereof, including a semiconductor substrate having a first area with a first trench formed therein and a second area with a second trench formed therein; a first sidewall oxide layer formed on the inner surface of the first trench; a second sidewall oxide layer, which is thinner than the first sidewall oxide layer, formed on the inner surface of the second trench; a liner formed on the surfaces of the first and second sidewall oxide layers; and a dielectric material that fills the first and second trenches.
Claims29
A semiconductor device having a shallow trench isolation (STI) structure, comprising:
- a semiconductor substrate having a first area with a first trench formed therein and a second area with a second trench formed therein;
- a first sidewall oxide layer formed on an inner surface of the first trench;
- a second sidewall oxide layer formed on an inner surface of the second trench, the second sidewall oxide layer having a thickness less than the first sidewall oxide layer;
- a liner formed on surfaces of the first and second sidewall oxide layers;
- and
- a dielectric material that fills the first and second trenches.
A semiconductor device having an STI structure, comprising:
- a semiconductor substrate having core and periphery areas in which a P-FET and other circuit devices are formed, a cell area in which memory devices are formed, and first and second trenches for isolating devices formed in the cell area and core and periphery areas;
- a first sidewall oxide layer formed on an inner surface of the first trench;
- a second sidewall oxide layer formed on an inner surface of the second trench, the second sidewall oxide layer having a thickness less than the first sidewall oxide layer;
- a liner formed on surfaces of the first and second sidewall oxide layers;
- and
- a dielectric material that fills the first and second trenches.
A semiconductor device having a shallow trench isolation (STI) structure, comprising:
- a semiconductor substrate having a first area with a first trench formed therein and a second area with a second trench formed therein;
- a first sidewall oxide layer formed on an inner surface of the first trench;
- a second sidewall oxide layer formed on an inner surface of the second trench, the second sidewall oxide layer having a thickness less than the first sidewall oxide layer;
- a liner formed on surfaces of the first and second sidewall oxide layers;
- and
- a dielectric material that fills the first and second trenches.
Dependencies are inferred from the claim text.