Non-volatile semiconductor memory devices with control gates overlapping pairs of floating gates

A non-volatile semiconductor memory device of the present invention comprising:

• a first conductivity type of a semiconductor substrate having separately formed first active areas, second active areas formed between, and integrally connected to, parts of both sides of, pairs of the first active areas, and field areas formed with a field insulating layer for isolating the first active areas;
• first gate insulating layers respectively formed at the substrate of the first and second active areas;
• floating gates arranged at the first gate insulating layer in a predetermined interval;
• oxide layers respectively formed at the upper surfaces of the floating gates;
• second gate insulating layers, to be used as tunneling insulating layers, formed at the lateral surfaces of the floating gates;
• control gates, each of which overlaps a pair of floating gates out of the floating gates;
• and
• a second conductive type of active source areas formed at the first active areas, a part of which is overlapped at the same portion of the floating gates, and at a part of the neighboring first active areas, wherein the second active areas are integrally connected between the source areas to prevent the neighboring source areas of the same source line, out of the source areas, from being isolated by the field insulating layer and to make them electrically connected.

A nonvolatile integrated circuit memory device, comprising:

• first and second EEPROM cells disposed side-by-side at spaced locations in a semiconductor substrate, said first and second EEPROM cells having first and second source regions of first conductivity type therein, respectively;
• a trench isolation region disposed in the semiconductor substrate and extending between said first and second EEPROM cells;
• and
• a buried source region of first conductivity type that extends in the semiconductor substrate at a location extending adjacent a bottom of said trench isolation region and electrically connects the source region of said first EEPROM cell to the source region of said second EEPROM cell.

A non-volatile semiconductor memory device comprising:

• a semiconductor substrate;
• a gate insulating layer formed on the semiconductor substrate;
• floating gates arranged at predetermined intervals on the gate insulating layer;
• oxide layers, each of which is on an upper surface of a respective floating gate, the oxide layers having a greater thickness over a middle portion of the upper surface of the floating gates than along an edge portion of the upper surface of the floating gates;
• a tunneling insulating layer on lateral surfaces of the floating gates, wherein the thickness of the second gate insulating layer is substantially less than the thickness of the oxide layers over the middle portion of the upper surface of the floating gates;
• and
• control gates, each of which overlaps a pair of floating gates out of the floating gates.

A non-volatile semiconductor memory device comprising:

• a semiconductor substrate;
• a first gate insulating layer formed on the semiconductor substrate;
• floating gates arranged at predetermined intervals on the first gate insulating layer;
• oxide layers, each of which is on an upper surface of respective floating gates;
• control gates, each of which overlaps a pair of floating gates out of the floating gates;
• source regions in the semiconductor substrate, each of the source regions adjacent to one of the pair of floating gates out of the floating gates;
• and
• drain regions in the semiconductor substrate, each of the drain regions self-aligned to the other one of the pair of floating gates out of the floating gates.