Split gate type memory cell having gate insulating layers appropriately regulated in thickness and process of fabrication thereof
AssigneeNEC Corporation
InventorKenji Saito
Life of this patent
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Abstract
A split gate type memory cell is a series combination of a stacked gate type memory transistor and a selecting field effect transistor, and the control gate insulating layer and the selecting gate oxide layer are to be thick and thin, respectively; an upper silicon oxide layer and the selecting gate oxide layer are thermally grown after deposition of a lower silicon oxide layer and a silicon nitride layer on the floating gate electrode, and the previous deposition of the lower silicon oxide layer/the silicon nitride layer and the thermal oxidation independently regulate the control gate insulating layer and the selecting gate oxide layer to appropriate thicknesses.
Claims11
A process for fabricating a split gate type memory cell on an active region of a semiconductor substrate, comprising the steps of:
- a) forming a first impurity region and a second impurity region spaced from each other in said active region;
- b) covering a part of said first impurity region and a sub-region of said active region adjacent to said first impurity region with a first gate insulating layer;
- c) successively depositing a first conductive material, a first insulating material and silicon nitride for forming a first conductive material layer, a first insulating material layer and a silicon nitride layer on said first gate insulating layer;
- d) patterning said first conductive material layer, said first insulating material layer and said silicon nitride layer into a first conductive stripe, a first insulating sub-layer laminated on said first conductive stripe and a second insulating sub-layer laminated on said first insulating sub-layer;
- e) covering said second insulating sub-layer and another sub-region of said active region adjacent to said sub-region with a second insulating layer of a second insulating material for forming a second gate insulating layer on said first conductive stripe and a third gate insulating layer on said another sub-region;
- f) forming a second conductive stripe of a second conductive material extending over said second gate insulating layer and said third gate insulating layer for providing a control gate electrode on said second gate insulating layer and a selecting gate electrode on said third gate insulating layer;
- and
- g) selectively etching said first conductive stripe for forming a floating gate electrode between said first gate insulating layer and said second gate insulating layer.
Dependencies are inferred from the claim text.