SAC method for embedded DRAM devices

A method for fabricating an integrated circuit device having logic and memory cells on a single semiconductor substrate comprising:

• forming isolation regions in and on said semiconductor substrate separating active areas wherein said active areas comprise at least one logic area and at least one memory area;
• forming gate electrode stacks in said active areas wherein said gate electrode stacks comprise a first polysilicon layer, an overlying silicide layer, an overlying first oxide layer, and a topmost capping silicon nitride layer;
• covering said semiconductor substrate and said gate electrode stacks with a photoresist layer;
• covering said memory areas with a mask;
• exposing said photoresist layer in said logic areas not covered by said mask to a low energy exposure;
• partially developing away exposed said photoresist layer in said logic areas to a height approximately equal to the height of said topmost capping silicon nitride layer;
• etching away said topmost capping silicon nitride layer in said logic areas;
• thereafter removing said photoresist layer in both said logic areas and said memory areas;
• implanting lightly doped regions in both said logic areas and said memory areas;
• depositing a first silicon nitride layer over said semiconductor substrate and said gate electrode stacks;
• etching said first silicon nitride layer in said logic areas to form silicon nitride sidewalls on said gate electrode stacks in said logic areas;
• thereafter implanting heavily doped source and drain regions in said logic areas;
• depositing a second silicon nitride layer overlying said gate stacks and said silicon nitride sidewalls in said logic areas and overlying said first silicon nitride layer in said memory areas;
• covering said gate stacks with a second oxide 40 layer;
• forming polysilicon plugs in said memory areas wherein said polysilicon plugs extend through said second oxide layer to an underlying said lightly doped region;
• covering said second oxide layer and said polysilicon plugs with a third oxide layer;
• forming a capacitor wherein said capacitor extends through said third oxide layer to contact one of said polysilicon plugs;
• covering said third oxide layer and said capacitor with a fourth oxide layer;
• simultaneously etching contact openings through said second, third, and fourth oxide layers in both said logic areas and said memory areas wherein said etching said contact openings has an etch stop;
• and filling said contact openings with a first metal layer to complete fabrication of said integrated circuit device having logic and memory cells on a single silicon chip.

A method for fabricating an integrated circuit device having logic and memory cells on a single semiconductor substrate comprising:

• forming isolation regions in and on said semiconductor substrate separating active areas wherein said active areas comprise at least one logic area and at least one memory area;
• forming gate electrode stacks in said active areas wherein said gate electrode stacks comprise a first polysilicon layer, an overlying silicide layer, an overlying first oxide layer, and a topmost capping silicon nitride layer;
• covering said semiconductor substrate and said gate electrode stacks with a photoresist layer;
• covering said memory areas with a mask;
• exposing said photoresist layer in said logic areas not covered by said mask to a low energy exposure;
• partially developing away exposed said photoresist layer in said logic areas to a height approximately equal to the height of said topmost capping silicon nitride layer;
• etching away said topmost capping silicon nitride layer in said logic areas;
• thereafter removing said photoresist layer in both said logic areas and said memory areas;
• implanting lightly doped regions in both said logic areas and said memory areas;
• depositing a first silicon nitride layer over said semiconductor substrate and said gate electrode stacks;
• etching said first silicon nitride layer in said logic areas to form silicon nitride sidewalls on said gate electrode stacks in said logic areas;
• thereafter implanting heavily doped source and drain regions in said logic areas;
• depositing a second silicon nitride layer overlying said gate stacks and said silicon nitride sidewalls in said logic areas and overlying said first silicon nitride layer in said memory areas;
• covering said gate stacks with a second oxide layer;
• opening self-aligned contact openings to an underlying said lightly doped region between said gate electrode stacks in said memory areas;
• filling said self-aligned contact openings with a polysilicon layer;
• removing said polysilicon layer except where it fills said self-aligned contact openings to form polysilicon plugs;
• covering said second oxide layer and said polysilicon plugs with a third oxide layer;
• forming a capacitor wherein said capacitor extends through said third oxide layer to contact one of said polysilicon plugs;
• covering said third oxide layer and said capacitor with a fourth oxide layer;
• simultaneously etching contact openings through said second, third, and fourth oxide layers in both said logic areas and said memory areas wherein said etching said contact openings has an etch stop;
• and
• filling said contact openings with a first metal layer to complete fabrication of said integrated circuit device having logic and memory cells on a single silicon chip.