Integration of an ion implant hard mask structure into a process for fabricating high density memory cells

A process comprising:

• depositing a hard mask overlying an ONO layer, the ONO layer is formed over a semiconductor substrate having a principal surface, and the ONO layer has a first silicon dioxide layer overlying the semiconductor substrate, a silicon nitride layer overlying the first silicon dioxide layer overlying the silicon nitride layer;
• patterning the hard mask;
• implanting the semiconductor substrate with a p-type dopant at an angle substantially normal to the principal surface of the semiconductor substrate, wherein the hard mask is used as an ion implant mask;
• annealing the semiconductor substrate upon implanting the semiconductor substrate with a p-type dopant;
• and
• implanting the semiconductor substrate with an n-type dopant, wherein the hard mask is used as an ion implant mask.

A process for fabricating a memory cell comprising:

• providing a semiconductor substrate having a principal surface;
• forming an ONO layer over the semiconductor substrate, the ONO layer having a first silicon dioxide layer overlying the semiconductor substrate, a silicon nitride layer overlying the first silicon dioxide layer, and a second silicon dioxide layer overlying the silicon nitride layer;
• depositing a hard mask overlying the ONO layer;
• patterning the hard mask;
• implanting the semiconductor substrate with a p-type dopant at an angle substantially normal to the principal surface of the semiconductor substrate;
• annealing the semiconductor substrate upon implanting the semiconductor substrate with a p-type dopant;
• and
• implanting the semiconductor substrate with an n-type dopant at an angle substantially normal to the principal surface of the semiconductor substrate.