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US 6,486,012 B1Granted
Semiconductor device having field effect transistors different in thickness of gate electrodes and process of fabrication thereof
AssigneeNEC Corporation
InventorAtsuki Ono
Life of this patent
Estimating the term…
Abstract
An n-channel type field effect transistor and a p-channel type field effect transistor are fabricated on a p-type well and an n-type well, respectively, and the arsenic-doped gate electrode of the n-channel type field effect transistor is thinner than the boron-doped gate electrode of the p-channel type field effect transistor so that the arsenic and the boron are appropriately diffused in the gate electrodes during a rapid annealing.
Claims7
A process for fabricating a semiconductor device, comprising the steps of:
- forming a p-type region and an n-type region isolated from each other by means of an insulating layer in a surface region of a semiconductor substrate;
- forming a first insulating layer on said semiconductor substrate;
- forming a polysilicon layer on said first insulating layer;
- forming a second insulating layer on said polysilicon layer;
- patterning said second insulating layer and said polysilicon layer over said p-type and n-type regions into gate structures of n-channel/p-channel insulating gate type field effect transistors;
- depositing a third insulating layer over the entire surface of said semiconductor substrate;
- masking a region assigned to said p-channel transistor of said both transistors with a first masking layer;
- removing said second insulating layer of said gate structure of said n-channel transistor of said both transistors so as to expose said polysilicon layer;
- decreasing the thickness of said exposed polysilicon layer;
- introducing an n-type impurity into the region assigned to said n-channel transistor under the condition that said region assigned to said p-channel transistor is covered with said first mask layer;
- masking said region assigned to said n-channel transistor with a second mask layer;
- and
- introducing a p-type impurity into said region assigned to said p-channel transistor.
10 more elements
A process of fabricating a semiconductor device comprising the steps of:
- forming a p-type region and an n-type region isolated from each other by means of an insulating layer in a surface region of a semiconductor substrate;
- forming a first insulating layer on said semiconductor substrate;
- forming a polysilicon layer on said first insulating layer;
- forming a second insulating layer on said polysilicon layer;
- patterning said second insulating layer and said polysilicon layer over said p-type and n-type regions into gate structures of n-channel/p-channel insulating gate type field effect transistors;
- forming wall spacers formed on side surfaces of said gate structures of n-channel/p-channel insulating gate field effect transistors wherein said insulating side wall spacers are substantially equal in their width;
- depositing a third insulating layer over the entire surface of said semiconductor substrate;
- masking a region assigned to p-channel transistor of said both transistors with a first masking layer;
- removing said second insulating layer of said gate structure of said n-channel transistor of said both transistors so as to expose said polysilicon layer;
- introducing an n-type impurity into the region assigned to said n-channel transistor under the condition that said region assigned to said p-channel transistor is covered with said first mask layer;
- masking said region assigned to said n-channel transistor with a second mask layer;
- and introducing a p-type impurity into said region assigned to said p-channel transistor.
9 more elements
Dependencies are inferred from the claim text.