US 6,486,007 B2 · Method of fabricating a memory cell for a static random access memory

Abstract

A method is disclosed for a memory cell for a static random access memory. The memory cell includes a pair of cross-coupled CMOS logic inverters that are connected together to form a latch, and a pair of p-channel transmission gate transistors that are connected to the logic inverters for selectively providing access to the latch. The layout of the memory cell includes a rectangular active area in which the p-channel transistors of the memory cell are located. The rectangular active area abuts a similar active area of an adjacent memory cell along a row of memory cells so as to form a single rectangular active area for the p-channel memory cell transistors. The rectangular active area reduces the occurrence of fabrication-related phenomena that adversely effect the performance of the memory cell.

Claims24

Dependent claims

A method of fabricating a memory cell on a semiconductor substrate, comprising the steps of:

defining a first active area on the semiconductor substrate for p-channel transistors of the static memory cell having a substantially rectangular shape;
defining a second active area on the semiconductor substrate for n-channel transistors of the static memory cell having a substantially rectangular shape;
depositing an insulator layer over the first and second active areas of the semiconductor substrate;
depositing and patterning a polysilicon layer over the semiconductor substrate so as to form gate regions of two n-channel transistors in the second active area and four p-channel transistors in the first active area;
forming source and drain diffusion regions for the p-channel transistors;
forming source and drain diffusion regions for the n-channel transistors;
and
forming one or more metal layers over the semiconductor substrate so as to connect two of the four p-channel transistors and the n-channel transistors together to form a pair of cross-coupled inverters, and connect the other of the two four p-channel transistors to the cross-coupled inverters to form transmission gate transistors of the memory cell;
wherein the step of defining the first active area defines the first active area so as to abut one or more first active areas of one or more other memory cells defined on the semiconductor substrate, the abutted active areas forming a single substantially rectangular active area.

6 more elements

A method of fabricating a memory device on a semiconductor substrate, comprising the steps of:

defining one or more first active areas having a substantially rectangular shape on the semiconductor substrate for transistors of a first type in a row of memory cells;
defining one or more second active areas having a substantially rectangular shape on the semiconductor substrate for transistors of a second type in the row of memory cells;
depositing an insulator layer over the one or more first active areas and the one or more second active areas of the semiconductor substrate;
depositing and patterning a polysilicon layer over the semiconductor substrate so as to form gate regions of the transistors of the second type in the one or more second active areas and gate regions of the transistors of the first type in the one or more first active areas;
forming source and drain diffusion regions for the transistors of the first type in the one or more first active areas;
forming source and drain diffusion regions for the transistors of the second type in the one or more second active areas;
and
forming one or more electrically conductive layers over the semiconductor substrate so as to connect together transistors of the first type in the one or more first active areas and transistors of the second type in the one or more second active areas to form pairs of cross-coupled inverters for memory cells in the row;
wherein the step of forming one or more electrically conductive layers connects transistors of the first type in the one or more first active areas to the cross-coupled inverters to form transmission gate transistors for memory cells in the row.

6 more elements

A method of fabricating a memory cell on a semiconductor substrate, comprising the steps of:

defining a first active area on the semiconductor substrate having a substantially rectangular shape for transistors of the static memory cell having a first conductivity type;
defining a second active area on the semiconductor substrate having a substantially rectangular shape for transistors of the static memory cell having a second conductivity type;
depositing an insulator layer over the first and second active areas of the semiconductor substrate;
depositing and patterning a polysilicon layer over the semiconductor substrate so as to form gate regions of the transistors of the first conductivity type in the first active area and the transistors of the second conductivity type in the second active area;
forming source and drain diffusion regions for the transistors of the first conductivity type;
forming source and drain diffusion regions for the transistors of the second conductivity type;
and
forming one or more layers of electrically conductive material over the semiconductor substrate so as to connect together transistors of the first conductivity type and transistors of the second conductivity type to define a pair of cross-coupled inverters of the memory cell;
wherein the step of forming one or more layers of electrically conductive material connects transistors of the first type to the cross-coupled inverters to define transmission gate transistors of the memory cell.

6 more elements

Dependencies are inferred from the claim text.

Method of fabricating a memory cell for a static random access memory

Life of this patent

Method of fabricating a memory cell for a static random access memory

Life of this patent

Abstract

Claims24