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US 6,486,002 B1Granted
Tape design to reduce warpage
AssigneeLSI Logic Corporation
InventorsQwai H. Low, Ramaswamy Ranganathan, Sengsooi Lim
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Abstract
An improved tape substrate design for a semiconductor package is disclosed. The tape substrate semiconductor package includes a plurality of die pads, a plurality of vias, and a pattern of metal traces interconnected between the die pads and the vias to form circuitry on the tape substrate. According to the method and apparatus of the present invention an extra metal layer is added at the circuitry to increase rigidity of the tape substrate, thereby reducing warpage without adding to the thickness of the tape substrate package.
Claims5
A tape substrate semiconductor package, comprising
- a plurality of die pads;
- a plurality of vias;
- a pattern of metal traces interconnected between the die pads and the vias to form circuitry on the tape substrate;
- and
- a metal layer added between the circuitry to increase rigidity of the tape substrate, thereby reducing warpage without adding to the thickness of the tape substrate package.
2 more elements
Dependencies are inferred from the claim text.