Method of producing phase masks in an automated layout generation for integrated circuits

A method of producing phase masks for automatically generating a layout for an integrated circuit, the method which comprises;

• compacting a layout of an integrated circuit by processing a distance graph by applying a longest path algorithm;
• allocating a respective phase to at least some of a plurality of polygons in the layout for generating a phase mask by,
• if a longest path can be further shortened with the longest path algorithm, then allocating the respective phase to given ones of the polygons having no allocated phase yet, and
• if a minimum distance between specific ones of the polygons having an identical phase is achieved, then allocating respective different phases to the specific ones of the polygons;
• and
• performing the allocating step during the processing of the distance graph by applying the longest path algorithm.