Method, apparatus, and program product for laying out capacitors in an integrated circuit

A processing system for use in laying out a capacitor arrangement in a free area of an integrated circuit chip to increase on-chip capacitance, the system comprising:

• (a) a height input arrangement for inputting a capacitor arrangement height dimension range between a maximum height dimension and a minimum height dimension;
• (b) a width input arrangement for inputting an expression defining a plurality of capacitor arrangement width dimensions, the capacitor arrangement width dimensions being transverse to the maximum height dimension;
• and
• (c) a sizing processor for applying the capacitor height dimension range and the plurality of capacitor arrangement width dimensions to select a particular capacitor arrangement for the free area, the selected capacitor arrangement comprising an arrangement with the largest area which is accommodated within the free area subject to the capacitor height dimension range and the plurality of capacitor arrangement width dimensions.

A computer program product for use in laying out a capacitor arrangement in a free area of an integrated circuit chip to increase on-chip capacitance, the computer program product comprising computer readable program code stored on a computer readable storage medium and including:

• (a) height input program code for receiving from an input arrangement a capacitor arrangement height dimension range between a maximum height dimension and a minimum height dimension;
• (b) width input program code for receiving from the input arrangement an expression defining a plurality of capacitor arrangement width dimensions, the capacitor arrangement width dimensions being transverse to the maximum height dimension;
• and
• (c) sizing program code for applying the capacitor arrangement height dimension range and the plurality of capacitor arrangement width dimensions to select a particular capacitor arrangement for the free area, the selected capacitor arrangement comprising an arrangement with the largest area which is accommodated within the free area subject to the capacitor arrangement height dimension range and the plurality of capacitor arrangement width dimensions.