Contactless flash memory with shared buried diffusion bit line architecture

An integrated circuit comprising:

• a bit line;
• and
• a bank of memory cells, wherein the bank of memory cells comprises:
• a diffused bit line that is continuous between a first end and a second end in a substrate;
• a diffused source line in the substrate;
• a plurality of memory cells formed in an on the substrate, wherein portions of the diffused bit line and the diffused source line form drain/source regions of the memory cells;
• a first bank select device that is between the bit line and the diffused bit line, wherein when activated, the first bank select conduct conducts a first current between the bit line and the first end of the diffused bit line;
• and
• a second bank select device that is between the bit line and the diffused bit line, wherein when activated, the second bank select device conducts a second current between the bit line and the second end of the diffused bit line, wherein
• each of the first and second bank select devices has a size such that during programming, each of the first current and the second current that flows is insufficient by itself to program the memory cell in a required programming time, and a combination of the first and second currents flowing through the first and second bank select devices during programming is sufficient to program the memory cell in the required programming time.

An integrated circuit comprising:

• a bit line;
• end
• a bank of memory cells, wherein the bank of memory cells comprises:
• a first diffused bit line that is continuous between a first end;and a second end in a substrate;
• a second diffused bit line that is continuous between a first end and a second end in the substrate;
• a diffused source line in the substrate;
• a first plurality of memory cells formed in an on the substrate, wherein portions of the first diffused bit line and the diffused source line form drain/source regions of the memory cells;
• a second plurality of memory cells formed in and on the substrate, wherein portions of the second diffused bit line and the diffused source line form drain/source regions of the memory cells in the second plurality;
• a first bank select device that when activated, conducts a current that enters the first end of the first diffused bit line;
• a second bank select device that when activated, conducts a current that enters the second end of the first diffused bit line;
• a third bank select device that when activated, conducts a current that enters the first end of the second diffused bit line;
• a fourth bank select device that when activated, conducts a current that enters the second end of the second diffused bit line;
• a first contact connecting the bit line to the first and third bank select devices;
• and
• a second contact connecting the bit line to the second and fourth bank select devices.

A method for reading a memory cell in a contactless Flash memory, the method comprising:

• activating a word line associated with the memory cell to a level that enables a current flow through the memory cell from a diffused bit line to a diffused source line if the memory cell is in a first threshold voltage state but does not enable current flow if the memory cell is in a second threshold voltage state;
• and
• connecting a metal bit line to a first end and a second end of a diffused bit line associated with the memory cell;
• grounding the diffused source line;
• and
• sensing whether a current flows through the metal bit line.