Network of triacs with gates referenced with respect to a common opposite face electrode
AssigneeSGS-Thomson Microelectronics S.A.
InventorRobert Pezzani
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Abstract
The present invention relates to a triac network wherein each triac includes an N-type semiconductor substrate, containing a first thyristor comprised of NPNP regions and a second thyristor comprised of PNPN regions, and surrounded with a P-type deep diffusion. A P-type well contains an N-type region, on the front surface side. A first metallization corresponds to a first main electrode, a second metallization corresponds to a second main electrode, a third metallization covers the N-type region and is connected to a gate terminal, and a fourth metallization connects the P-type well to the upper surface of the deep diffusion.
Claims21
A method of controlling at least one triac, the at least one triac including a first triac having a first terminal formed on a first surface of the first triac and having second and control terminals formed on a second surface of the first triac that opposes the first surface of the first triac, the first terminal of the first triac being electrically coupled to a reference voltage terminal, the method comprising the steps of:
- receiving a first voltage on the second terminal of the first triac;
- and
- applying a first control voltage that is referenced to a voltage on the first terminal of the first triac to the control terminal of the first triac to initiate conduction between the first and second terminals of the first triac.
Dependencies are inferred from the claim text.