Semiconductor device with registration accuracy measurement mark

A semiconductor device comprising:

• a master pattern formed on a layer of said semiconductor device;
• said master pattern having a first offset value attributable to coma aberration based on a width of said master pattern;
• and
• a registration accuracy measurement mark pattern for measuring an error in registration relative to lithography steps;
• said registration accuracy measurement mark pattern having a second offset value attributable to coma aberration based on a width of said registration accuracy measurement mark pattern;
• wherein;
• the width of said master pattern and the width of said registration accuracy measurement mark pattern are determined to allow a difference between said first offset value and said second offset value to be at most an allowable value, and
• the width of said registration accuracy measurement mark pattern is larger than the width of said master pattern by at least a prescribed value to ensure sufficient depth of focus when said master pattern and said registration accuracy measurement mark pattern are of different heights.