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AssigneeHitachi, Ltd.
InventorsTakuya Fukuda, Nobuyoshi Kobayashi, Yoshitaka Nakamura, Masayoshi Saito, Shinichi Fukada, Yoshifumi Kawamoto
Estimating the term…
The new structure of a memory cell which enables avoiding the problem of a step without increasing the number of processes, the structure of a semiconductor integrated circuit in which a common part of the same substrate in a manufacturing process is increased and the structure of the semiconductor integrated circuit which allows measures for environment obstacles without increasing the number of processes are disclosed. Memory cell structure in which a capacitor is formed in the uppermost layer of plural metal wiring layers by connecting the storage node of the capacitor to a diffusion layer via plugs and pads is adopted. It is desirable that a dielectric film formed in a metal wiring layer under the uppermost layer and a supplementary capacitor composed of a storage node and a plate electrode are connected to the capacitor. It is also desirable that the plate electrode of the capacitor covers the chip.
A semiconductor integrated circuit device in which plural memory cells each of which is constituted by combining a MOS field effect transistor comprised of one gate electrode and two diffusion layers (a drain area and a source area) and a capacitor for storing electric charges in which a dielectric film is held between a storage node and a plate electrode are arrayed in a matrix on a semiconductor substrate, a word line of wires from a predetermined external circuit to an individual one of said memory cells is arranged in a passivated insulating film layer, a bit line is arranged in a bit line layer and the other wires including a wire to a plate electrode and an internal wire between said transistor and said capacitor of an individual memory cell are arranged in plural metal wiring layers, wherein:
Dependencies are inferred from the claim text.