US 6,479,874 B2Granted

Semiconductor memory device having multilevel memory cell and method of manufacturing the same

AssigneeNEC Corporation

InventorsKenji Hibino, Masao Kunitou, Kazuyuki Yamasaki, Tetsuji Togami, Hironori Sakamoto, Kiyokazu Hashimoto

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Abstract

A semiconductor ROM device which enables to obtain a reference current which can securely distinguish data stored in a memory cell in a multilevel mask ROM for storing multilevel data of three or more levels per memory cell. The device comprises a memory cell in which a threshold voltage is set up corresponding to an amount of ions injected to a channel region of a cell transistor and multilevel data of three or more levels are stored, a reference cell for generating the reference current for comparing with a current read out from the memory cell, and dummy cells disposed adjacent to the reference cell. In the channel region of the reference cell and the channel region of the dummy cell, ions are injected simultaneously to set up the equal threshold voltages both in the reference cell and the dummy cell.

Claims9

Dependent claims

A semiconductor read only memory (ROM) device comprising:

a semiconductor substrate;
a data memory cell provided on said semiconductor substrate, said data memory cell comprising a data cell transistor, said data cell transistor having a data cell transistor threshold voltage corresponding to a predetermined one of multilevel data of three or more levels that can be stored in said data memory cell, said data cell transistor threshold voltage causing a current level to flow from said data cell transistor during a data read operation;
a reference cell provided on said semiconductor substrate, said reference cell comprising a reference cell transistor having a reference cell threshold voltage corresponding to a predetermined one of said multilevel data of three or more levels, said reference cell being used for generating a reference current which is compared with said current read out from said data memory cell to discriminate the data stored in said data memory cell;
and
at least one dummy cell provided on said semiconductor substrate, each said dummy cell comprising a dummy cell transistor, said dummy cell transistor disposed adjacent to said reference cell transistor, said dummy cell transistor having a dummy cell threshold voltage corresponding to a predetermine d one of said multilevel data of three or more levels, wherein said dummy cell threshold voltage equals said reference cell threshold voltage.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/161,510Filed 28 Sep 1998
Priority: JP 9-2690531 Oct 1997
Published: US 2001/0042893 A122 Nov 2001
Granted: 12 Nov 2002
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

H10B 20/00
Read-only memory [rom] devices
G11C 11/5692
Using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency: read-only digital stores…
H10B 20/38
Having the source region and the drain region on the same level, e.g. lateral transistors: doping programmed, e.g. mask ROM
H10B
Electronic memory devices