US 6,479,863 B2 · Method and apparatus for injecting charge onto the floating gate of a nonvolatile memory cell

Abstract

A tunneling charge injector includes a conducting injector electrode, a grid insulator disposed adjacent the conducting injector electrode, a grid electrode disposed adjacent the grid insulator, a retention insulator disposed adjacent the grid electrode, and a floating gate electrode disposed adjacent the retention insulator. In the tunneling charge injector, charge is injected from the conducting injector electrode onto the floating gate. Electrons are injected onto the floating gate when the conducting injector electrode is negatively biased with respect to the grid electrode, and holes are injected onto the floating gate when the conducting injector electrode is positively biased with respect to the grid electrode. The tunneling charge injector is employed in a nonvolatile memory cell having a nonvolatile memory element with a floating gate such as a floating gate MOS transistor. In the nonvolatile memory cell, the floating gate of the tunneling charge injector is coupled to or forms a part of the floating gate of the nonvolatile memory element. The tunneling charge injector is employed to inject charge onto the floating gate of the nonvolatile memory element. A memory device includes an array of nonvolatile memory cells wherein each of the memory cells comprises a nonvolatile memory element with a floating gate such as a floating gate MOS transistor and a tunneling charge injector having a floating gate that is either coupled to the floating gate of the nonvolatile memory element or forms a portion of the floating gate of the nonvolatile memory element.

Claims43

Dependent claims

A nonvolatile memory cell comprising:

a floating gate MOS transistor including:
a semiconductor body having a doping of a first type;
first and second semiconductor regions having a doping of a second type, said first and second semiconductor regions spaced apart to form a channel region in between said first and second semiconductor regions in said semiconductor body;
a floating gate disposed above said channel region in said semiconductor body;
a floating gate dielectric disposed between said floating gate and said semiconductor conductor body;
a control gate;
a control gate dielectric disposed between said control gate and said floating gate;
and
a tunneling charge injector including:
a conducting injector electrode from which charge is emitted;
a grid insulator disposed adjacent to said conducting injector electrode;
a grid electrode disposed adjacent to said grid insulator;
and
a retention insulator disposed adjacent to said grid electrode, wherein said floating gate is disposed adjacent to said retention insulator and said tunneling charge injector is disposed along a side of said floating gate and separated therefrom by said grid insulator, said grid electrode and said retention insulator.

11 more elements

A nonvolatile memory cell comprising:

a floating gate MOS transistor including:
a semiconductor body having a doping of a first type;
first and second semiconductor regions having a doping of a second type, said first and second semiconductor regions spaced apart to form a channel region in between said first and second semiconductor regions in said semiconductor body;
a floating gate disposed above said channel region in said semiconductor body;
a floating gate dielectric disposed between said floating gate and said semiconductor body;
a control gate;
and
a control gate dielectric disposed between said control gate and said floating gate;
a tunneling electron injector including:
a first conducting injector electrode from which electrons are emitted;
a first grid insulator disposed adjacent to said first conducting injector electrode;
a first grid electrode disposed adjacent to said first grid insulator;
and
a first retention insulator disposed adjacent to said first grid electrode, wherein said floating gate is disposed adjacent to said first retention insulator and said tunneling electron injector is disposed along a first side of said floating gate and separated therefrom by said first grid insulator, said first grid electrode and said first retention insulator;
and
a tunneling hole injector including:
a second conducting injector electrode from which holes are emitted;
a second grid insulator disposed adjacent to said second conducting injector electrode;
a second grid electrode disposed adjacent to said second grid insulator;
and
a second retention insulator disposed adjacent to said second grid electrode wherein said floating gate is disposed adjacent to said second retention insulator and said tunneling hole injector is disposed along a second side of said floating gate and separated therefrom by said second grid insulator, said second grid electrode and said second retention insulator.

18 more elements

A nonvolatile memory device comprising:

a plurality of nonvolatile memory elements arranged in a rectangular array of rows and columns, each of said plurality of nonvolatile memory elements including:
a floating gate MOS transistor having a source region and a drain region formed in a semiconductor body and spaced apart by a channel region, a floating gate disposed above said channel region, and a control gate for said floating gate;
and
a tunneling electron injector having a first conducting injector electrode, a first grid insulator disposed adjacent to said first conducting injector electrode, a first grid electrode disposed adjacent to said first grid insulator, and a first retention insulator disposed adjacent to said first grid electrode, wherein said floating gate is disposed adjacent to said first retention insulator and said tunneling electron injector is disposed along a first side of said floating gate and separated therefrom by said first grid insulator, said first grid electrode and said first retention insulator;
a tunneling hole injector having a second conducting injector electrode, a second grid insulator disposed adjacent to said second conducting injector electrode, a second grid electrode disposed adjacent to said second grid insulator, and a second retention insulator disposed adjacent to said second grid electrode, wherein said floating gate is disposed adjacent to said second retention insulator and said tunneling hole injector is disposed along a second side of said floating gate and separated therefrom by said second grid insulator, said second grid electrode and said second retention insulator;
a plurality of word lines, a separate one of said plurality of word lines coupled to said control gate of each of said plurality of nonvolatile memory cells in a same row;
a plurality of bit lines, a separate one of said plurality of bit lines coupled to said drain region of each of said plurality of nonvolatile memory cells in a same column;
a plurality of source lines, at least one of said plurality of source lines coupled to said source region of each of said plurality of nonvolatile memory cells in a same row;
a first plurality of injector lines, at least one of said first plurality of injector lines coupled to said first conducting injector electrode of each of said plurality of nonvolatile memory cells in a same row;
a first plurality of grid lines, at least one of said first plurality of grid lines coupled to said first grid electrode of each of said plurality of nonvolatile memory cells in a same column;
a second plurality of injector lines, at least one of said second plurality of injector lines coupled to said second conducting injector electrode of each of said plurality of nonvolatile memory cells in a same row;
and
a second plurality of grid lines, at least one of said second plurality of grid lines coupled to said second grid electrode of each of said plurality of nonvolatile memory cells in a same column.

10 more elements

Dependencies are inferred from the claim text.

Method and apparatus for injecting charge onto the floating gate of a nonvolatile memory cell

Life of this patent

Method and apparatus for injecting charge onto the floating gate of a nonvolatile memory cell

Life of this patent

Abstract

Claims43