Memory device with divided bit-line architecture

A memory circuit, comprising:

• a plurality of sub-arrays of memory cells, each sub-array having a plurality of bit lines each coupling to a plurality of memory cells;
• and
• a sense amplifier disposed between a first and a second sub-array and configured to couple to selected bit lines and permit other bit lines to couple to a plurality of metal lines;
• wherein a first pair of bit lines from said first sub-array is respectively coupled to a first pair of metal lines via said sense amplifier;
• and
• wherein a second pair of bit lines from said second sub-array is respectively coupled to a second pair of metal lines via said sense amplifier.

A memory circuit having a divided bit-line, shared sense amplifier architecture, comprising:

• a first bank and a second bank of memory sub-arrays, each memory sub-array having a plurality of bit lines extending therefrom;
• and
• a bank of sense amplifiers disposed between said first and second banks of memory sub-arrays and configured to be shared by said first and second banks of memory sub-arrays;
• wherein selected bit lines from said first bank of memory sub-arrays make contact with a plurality of metal lines which traverse along selected bit lines from said second bank of memory sub-array via said bank of sense amplifiers.

A memory circuit having a divided bit-line, shared sense amplifier architecture, comprising:

• a plurality of banks of memory sub-arrays, each sub-array having a plurality of bit lines;
• and
• a plurality of banks of sense amplifiers;
• wherein any two adjacent banks of memory sub-arrays share at least one bank of sense amplifiers;
• and
• wherein a first number of selected bit lines from a first bank of sub-array make contact with a plurality of metal lines traversing along a second number of selected bit lines from a second bank of sub-array adjacent to said first bank of sub-array.

An improved memory circuit having a divided bit-line, shared sense amplifier architecture, comprising:

• a first and a second memory sub-arrays positioned adjacent to one another;
• a sense amplifier disposed at a location between said first and second memory sub-arrays and configured to be shared by said first and second memory sub-arrays;
• and
• an equilibration circuit disposed at said location and configured to precharge selected bit lines from said first and second memory sub-arrays and a plurality of metal lines.