Pattern for routing power and ground for an integrated circuit chip

A power and ground routing pattern for an integrated circuit chip, comprising:

• an integrated circuit chip, wherein said integrated circuit chip has devices formed therein, a first number of signal wiring layers, and a circuit region partitioned into a second number of sub-block regions having spaces therebetween;
• a first cap dielectric layer formed on said integrated circuit chip thereby covering said first number of signal wiring layers;
• a first power wiring layer formed on said first cap dielectric layer;
• a second cap dielectric layer formed on said first power wiring layer;
• a second power wiring layer formed on said second cap dielectric layer;
• a plurality of first vias between said first power wiring layer and said second power wiring layer;
• a plurality of second vias between said first power wiring layer and said second power wiring layer;
• a first power bus electrode formed in said first power wiring layer wherein said first power bus electrode surrounds said circuit region and each of said sub-block regions;
• a second power bus electrode formed in said second power wiring layer wherein said second power bus electrode is directly under said first power bus electrode, surrounds said circuit region, and surrounds each of said sub-block regions;
• first distribution electrodes formed in said first power wiring layer electrically connected to said first power bus electrode wherein said first distribution electrodes supply the voltage on said first power bus electrode to each of said sub-block regions;
• second distribution electrodes formed in said second power wiring layer electrically connected to said first power bus electrode and said first distribution electrodes by means of said first vias wherein said second distribution electrodes supply the voltage on said first power bus electrode to each of said sub-block regions;
• third distribution electrodes formed in said second power wiring layer electrically connected to said second power bus electrode wherein said third distribution electrodes supply the voltage on said second power bus electrode to each of said sub-block regions;
• and
• fourth distribution electrodes formed in said first power wiring layer electrically connected to said second power bus electrode and said third distribution electrodes by means of said second vias wherein said fourth distribution electrodes supply the voltage on said second power bus electrode to each of said sub-block regions.