Thin film transistor, thin film transistor array substrate, liquid crystal display device, and electroluminescent display device

A thin film transistor array substrate comprising:

• an insulating substrate;
• a plurality of thin film transistors arranged in a predetermined pattern, each of the thin film transistors comprising a) a channel region comprising a high melting point region composed of a first semiconductor, b) a source region being in contact with the high melting point region of the channel region, the source region comprising a first low melting point region composed of a second semiconductor having a melting point lower than that of the first semiconductor, and the source region containing a first dopant, c) a source electrode electrically connected to the high melting point region of the channel region via the first low melting point region of the source region, d) a drain region being spaced apart from the source region and in contact with the high melting point region of the channel region, the drain region comprising a second low melting point region composed of a third semiconductor having a melting point lower than that of the first semiconductor, and the drain region containing a second dopant, e) a drain electrode electrically connected to the high melting point region of the channel region via the low melting point region of the drain region, and f) a gate electrode electrically insulated from the channel region, the source electrode, and the drain electrode, the gate electrode controlling an electric field applied to the channel region;
• a source line electrically connected to the source electrode;
• a drain line electrically connected to the drain electrode;
• and
• a gate line electrically connected to the gate electrode.

A liquid crystal display device comprising:

• an insulating substrate;
• a thin film transistor formed on the insulating substrate, the thin film transistor comprising a) a channel region comprising a high melting point region composed of a first semiconductor, b) a source region being in contact with the high melting point region of the channel region, the source region comprising a first low melting point region composed of a second semiconductor having a melting point lower than that of the first semiconductor, and the source region containing a first dopant, c) a source electrode electrically connected to the high melting point region of the channel region via the first low melting point region of the source region, d) a drain region being spaced apart from the source region and in contact with the high melting point region of the channel region, the drain region comprising a second low melting point region composed of a third semiconductor having a melting point lower than that of the first semiconductor, and the drain region containing a second dopant, e) a drain electrode electrically connected to the high melting point region of the channel region via the low melting point region of the drain region, and f) a gate electrode electrically insulated from the channel region, the source electrode, and the drain electrode, the gate electrode controlling an electric field applied to the channel region;
• a source line electrically connected to the source electrode;
• a drain line electrically connected to the drain electrode;
• a gate line electrically connected to the gate electrode;
• a display electrode formed on a surface of the insulating substrate and electrically connected to the drain line;
• a first liquid crystal alignment film covering the thin film transistors the source line, the drain line, the gate line, and the display electrode;
• an opposing substrate opposing the insulating substrate;
• an opposing electrode formed on the opposing substrate and opposing the display electrode;
• a second liquid crystal alignment film formed on the opposing substrate and covering the opposing electrode;
• a liquid crystal layer being in contact with the first liquid crystal alignment film and the second liquid crystal alignment film and sandwiched between the insulating substrate and the opposing substrate;
• and
• a sealing portion for sealing the liquid crystal layer, the sealing portion provided at a peripheral region of the insulating substrate and the opposing substrate.

An electroluminescent display device comprising:

• an insulating substrate;
• a thin film transistor formed on an insulating substrate, the thin film transistor comprising a) a channel region comprising a high melting point region composed of a first semiconductor, b) a source region being in contact with the high melting point region of the channel region, the source region comprising a first low melting point region composed of a second semiconductor having a melting point lower than that of the first semiconductor, and the source region containing a first dopant, c) a source electrode electrically connected to the high melting point region of the channel region via the first low melting point region of the source region, d) a drain region being spaced apart from the source region and in contact with the high melting point region of the channel region, the drain region comprising a second low melting point region composed of a third semiconductor having a melting point lower than that of the first semiconductor, and the drain region containing a second dopant, e) a drain electrode electrically connected to the high melting point region of the channel region via the low melting point region of the drain region, and f) a gate electrode electrically insulated from the channel region, the source electrode, and the drain electrode, the gate electrode controlling an electric field applied to the channel region;
• a source line electrically connected to the source electrode;
• a drain line electrically connected to the drain electrode;
• a gate line electrically connected to the gate electrode;
• a display electrode formed on a surface of the insulating substrate;
• an opposing electrode opposing the display electrode;
• and
• a light-emitting layer formed between the display electrode and the opposing electrode.