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US 6,477,075 B2Granted
Memory circuit/logic circuit integrated device capable of reducing term of works
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorTsukasa Ooishi
Life of this patent
Estimating the term…
Abstract
A memory circuit is connected to a logic circuit in a flip chip structure. The memory circuit is electrically connected with the logic circuit through an interface layer provided over a plurality of chips. The capacity of the memory connected to the logic circuit can be readily changed by simply changing the pattern of the interface, thereby reducing the term for developing a memory circuit/logic circuit integrated device.
Claims11
An integrated device comprising:
- a first circuit chip including a first circuit formed on a first major surface of a first semiconductor substrate, said first circuit having a plurality of first input/output nodes for electrically interfacing with the exterior of said first circuit chip;
- a second circuit chip including a second circuit formed on a second major surface of a second semiconductor substrate, said second major surface being face to face with said first major surface and said second circuit having a plurality of second input/output nodes for electrically interfacing with the exterior of said second circuit chip;
- and
- a connecting portion electrically connecting said plurality of first input/output nodes to said second input/output nodes respectively, said connecting portion including:
- a first connecting member for establishing electrical connections from said plurality of second input/output nodes, and
- a second connecting member, provided between said first connecting member and said plurality of first input/output nodes, for electrically connecting said first connecting member to said plurality of first input/output nodes.
3 more elements
Dependencies are inferred from the claim text.