Layout design method on semiconductor chip for avoiding detour wiring

A semiconductor device comprising:

• a first macro cell arranged in an interior area of a semiconductor chip or a functional block on said semiconductor chip;
• and
• a second macro cell arranged in a peripheral area or a functional block on said semiconductor chip, said second macro cell including an element over which wiring is prohibited to be laid;
• wherein said element is for writing information,
• wherein said first macro cell includes:
• a plurality of first circuits each having a same configuration;
• a redundant circuit having the same configuration as said first circuit;
• and
• a switching circuit for, in response to a switching signal, making one of said first circuits containing a defect out of use with making said redundant circuit in use, and
• wherein said second macro cell includes a second circuit having said element, said second circuit being for outputting a signal depending on written information in said element as a signal related to said switching signal.

A layout design method on a semiconductor chip for producing said semiconductor chip, comprising the steps of:

• arranging a first macro cell in an interior of said semiconductor chip of a functional block on said semiconductor chip, wherein the first macro cell includes:
• a plurality of first circuits each having a same configuration;
• a redundant circuit having the same configuration as said first circuit;
• and
• a switching circuit for, in response to a switching signal, making one of said first circuit containing a defect out of use with making said redundant circuit in use;
• and
• arranging a second macro cell in a peripheral area of said semiconductor chip or said functional area, said second macro cell being interconnected through wiring to said first macro cell, said second macro cell having an element over which wiring is prohibited to be laid, said second macro cell being separated from said first macro cell.