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US 6,476,498 B1Granted
Elimination of flux divergence in integrated circuit interconnects
AssigneeAdvanced Micro Devices, Inc.
InventorAmit P. Marathe
Life of this patent
Estimating the term…
Abstract
An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A dielectric layer is formed on the semiconductor substrate and an opening is formed in the dielectric layer. A barrier layer is deposited to line the opening which is optimized to reduce current crowding by resistance changes and/or being thicker at the bottom and sidewalls of a via. A conductor core is then deposited to fill the channel opening over the barrier layer.
Claims10
An integrated circuit comprising:
- a substrate having a device provided thereon;
- a dielectric layer formed on the substrate having an opening provided therein said opening is a dual damascene opening comprising a via opening and a channel opening;
- a barrier layer to line the opening, the barrier layer thicker in the via opening than in the channel opening wherein current crowding will be reduced and Joule heating will be reduced compared to the barrier layer in the via portion having the same thickness as in the channel opening and
- a conductor core filling the opening and connected to the device.
1 more element
An integrated circuit comprising:
- a semiconductor substrate having a semiconductor device provided thereon;
- a first channel dielectric layer over the semiconductor substrate;
- a first channel opening in the first channel dielectric layer;
- a first barrier layer to line the first channel opening;
- a first conductor core over the first barrier layer to fill the opening and connect to the semiconductor device;
- a via dielectric layer over the first channel dielectric layer;
- a second channel dielectric layer over the via dielectric layer;
- a via opening in the via dielectric layer and a second channel opening in the second channel dielectric layer;
- a second barrier layer to line the via opening and second channel opening, the second barrier layer thicker in the via opening than in the channel opening wherein current crowding will be reduced and Joule heating will be reduced compared to the second barrier layer in the via opening having the same thickness as in the second channel opening;
- and
- a second conductor core over the barrier layer to fill the via and second channel opening and connect to the semiconductor device.
8 more elements
Dependencies are inferred from the claim text.