Front stage process of a fully depleted silicon-on-insulator device and a structure thereof

A bottom level structure of a fully depleted SOI device, which is applicable to SOI substrate, comprising:

• an SOI substrate comprising an insulation layer and crystalline silicon layer above the insulation layer;
• an isolation layer in the crystalline silicon layer, wherein the isolation layer is connected to the insulation layer and defines a first-type MOS active region;
• a second-type doped epitaxial silicon layer formed above the crystalline layer in the first-type MOS active region, and
• a second-type lightly doped epitaxial silicon layer above the second-type doped epitaxial silicon layer, wherein a doping concentration of the second-type lightly doped epitaxial silicon layer is far less than that of the second-type doped epitaxial silicon layer and the second-type lightly doped epitaxial silicon layer has a special profile caused by a diffusion of dopant from the second-type lightly doped epitaxial silicon layer.