Method and structure for textured surfaces in floating gate tunneling oxide devices

A transistor, comprising:

• a first interface having spaced source and drain regions and a body region therebetween on a first portion of the first interface, the first interface having a micro-roughened surface on the first portion of the first interface, the micro-roughened surface including an array of asperities, each asperity having a top surface, the asperities in the array of asperities having an average density of 1012/cm2;
• a second interface adjacent to the first interface;
• a third interface adjacent to the second interface;
• and
• a fourth interface adjacent to the third interface.

A memory array of non volatile memory cell structures, comprising:

• a number of floating gate tunneling oxide (FLOTOX) transistors, wherein each FLOTOX transistor comprises:
• a substrate having a first source/drain region, a second source/drain region, and a body region, the substrate having a textured surface, the textured surface including an array of microtips, each microtip having a top surface, the microtips in the array of microtips having an average density of 1012/cm2;
• a tunnel oxide layer formed on the textured surface of the substrate;
• a first conductive layer formed on the tunnel oxide layer;
• an insulator layer formed on the first conductive layer;
• and
• a second conductive layer formed on the insulator layer;
• and
• a number of wordlines, wherein each wordline couples the second conductive layer for a number of FLOTOX transistors;
• a number of bitlines, wherein each bitline couples the second source/drain region for a number of FLOTOX transistors;
• a number of sense amplifiers, wherein each sense amplifier couples to a select number of the number of bitlines;
• and
• a number of sourcelines, wherein each sourceline couples a first source/drain region for a number of FLOTOX transistors.

An information handling system, comprising:

• a memory array, wherein the memory array comprises:
• a number of floating gate tunneling oxide (FLOTOX) transistors, wherein each FLOTOX transistor comprises:
• a substrate, the substrate having a first source/drain region, a second source/drain region, and a body region, the substrate having a textured surface, the textured surface including an array of microtips, each microtip having a top surface, and wherein the microtips in the array of microtips have an average density of 1012/cm2;
• a tunnel oxide layer formed on the textured surface of the substrate;
• a first conductive layer formed on the tunnel oxide layer;
• an insulator layer formed on the first gate;
• and
• a second conductive layer formed on the insulator layer;
• a number of wordlines, wherein each wordline couples the second conductive layer for a number of FLOTOX transistor;
• a number of bitlines, wherein each bitline couples the second source/drain region for a number of FLOTOX transistors;
• a number of sense amplifiers, wherein each sense amplifier couple to a selected number of the number of bitlines;
• and
• a number of sourcelines, wherein each sourceline couples a first source/drain region for a number of FLOTOX transistors;
• a central processing unit;
• and
• a system bus, wherein the system bus couples the memory array to the central processing unit.

A non volatile memory cell structure, comprising:

• a substrate having a textured surface, the textured surface including an array of microtips having an average density of 1012/cm2 and an average height of 7 nanometers;
• a tunnel oxide layer formed on the textures surface of the substrate;
• a first gate formed on the tunnel oxide layer;
• an insulator formed on the first gate;
• and
• a second gate formed on the insulator.

A non volatile memory cell structure, comprising:

• a substrate having a textured surface, the textured surface including an array of microtips having an average density of 1012/cm2, each microtip having a top surface with an average diameter of 0.5 nanometer;
• a tunnel oxide layer formed on the textures surface of the substrate;
• a first gate formed on the tunnel oxide layer;
• an insulator formed on the first gate;
• and
• a second gate formed on the insulator.

A non volatile memory cell structure, comprising:

• a substrate having a textured surface, the textured surface including an array of microtips having an average density of 1012/cm2 and having an average center to center spacing of the microtips of 20 nanometers;
• a tunnel oxide layer formed on the textures surface of the substrate;
• a first gate formed on the tunnel oxide layer;
• an insulator formed on the first gate;
• and
• a second gate formed on the insulator.

A transistor, comprising:

• a first interface including spaced first and second source/drain regions and a body region therebetween on a first portion of the first interface, the first portion including a micro-roughened surface having an array of asperities, each asperity having a top surface, the array of asperities having:
• an average density of 1012/cm2,
• an average height of 7 nanometers (nm),
• an average diameter at the top surface of 0.5 nm, and
• a center to center spacing of 20 nm;
• a second interface on the first interface;
• a third interface on the second interface;
• and
• a fourth interface on the third interface.

A memory device, comprising:

• bit lines;
• source lines;
• and an array of memory structures connected to the bit lines and the source lines, a memory structure of the array of memory structures includes:
• a substrate having a first source/drain region, a second source/drain region, and a body region, the substrate having a textured surface, the textured surface including an array of microtips, the microtips in the array of microtips having an average density of 1012/cm2;
• a tunnel oxide layer formed on the textured surface of the substrate;
• a first conductive layer formed on the tunnel oxide layer;
• an insulator layer formed on the first conductive layer;
• and
• a second conductive layer formed on the insulator layer.