Crown or stack capacitor with a monolithic fin structure

A semiconductor device comprising:

• a doped semiconductor substrate with a top surface,
• a plurality of counterdoped regions formed in the doped semiconductor substrate,
• four gate electrode/conductor stacks formed spaced apart on the surface of the substrate including two inner stacks and two outer stacks with each of the outer stacks formed above one of the plurality of counterdoped regions and the stacks being insulated by sidewall spacers and at least one dielectric cap layer,
• each of a pair of conductive plugs being formed over one of the counterdoped regions between an inner stack and an outer stack, with the conductive plugs being in direct contact with respective ones of the counter doped regions, the conductive plugs extending between the silicon dioxide spacers,
• a planarizing insulating layer formed surrounding the conductive plugs and covering exposed surface of the spacers and the cap layer over the gate electrode/conductor stacks having spacers on the sides thereof,
• a conductive pad formed directly on top of each of the conductive plugs,
• each of a plurality of monolithic conductive cores formed over the conductive plugs, with each of the plurality of hollow conductive cores formed with a pattern of a plurality of cantilevered ribs projecting from the hollow conductive core with undercut edges and the capacitor core having a top surface, and
• the conductive pads being spaced apart between the monolithic capacitor cores from adjacent monolithic capacitor cores with the planarizing insulating layer being exposed between the conductive pads.