Self-aligned recessed container cell capacitor

A memory structure comprising:

• a semiconductor substrate having a top surface and having a trench therein that includes a bottom surface intersecting with opposing side walls that extend to the top surface of the semiconductor substrate;
• an insulator extending from the bottom surface of the trench to a top surface that is not above the trench, said insulator making contact with both of the opposing side walls of the trench,;
• a first container cell within said trench;
• a second container cell within said trench and separated from the first container cell by the insulator, wherein each of the first and second container cells is completely defined by a surface and has therein:
• a storage node upon one of said opposing side walls of the trench and continuously covering a majority of the surface thereof;
• and
• a cell dielectric upon the storage node;
• and
• a cell plate upon each said cell dielectric and extending to make contact with the top surface of the insulator.

In a memory structure that includes a semiconductor substrate having a top surface and an array of memory elements, each memory element in the array including an active area in the semiconductor substrate, a bit line contact electrically connected to the active areas a container cell, a storage node, a cell dielectric, and a cell plate, the memory structure comprising:

• a plurality of trenches within the semiconductor substrate each having:
• opposing side walls that extend to the top surface of the semiconductor substrate;
• an insulator disposed therein having a top surface that is not above the respective trench, said insulator making contact with both of the opposing side walls;
• and
• two of said container cells therein;
• wherein:
• each said storage node is within a respective one said container cells;
• each said storage node terminates at the top surface of the semiconductor substrate and extends upon one of the opposing side walls;
• each said cell dielectric is upon one of said storage nodes;
• each said bit line contact is upon the top surface of the semiconductor substrate and electrically connected to one of the active areas;
• and
• said cell plate extends above the top surface of the semiconductor substrate.

A memory structure including a plurality of memory cells each including a cell plate upon a cell dielectric which is upon a storage node, the memory structure further comprising:

• a substrate having a substrate surface;
• a first recess having opposing side walls extending from the substrate surface;
• a dielectric material within and not extending above the first recess, said dielectric material contacting the opposing side walls;
• and
• a plurality of second recesses each having a recess surface defined by:
• one of the opposing side walls;
• and
• the dielectric material;
• wherein each said storage node is within a respective one of said second recesses and is upon a majority of the recess surface thereof.

In a memory device that includes a semiconductor substrate having a plurality of active areas therein and a top surface thereon, a memory structure comprising:

• a pair of bit line contacts each contacting:
• a bit line;
• and
• one of the active areas at the top surface of the semiconductor substrate;
• a first recess defined by a bottom surface within the semiconductor substrate that litersects opposing side walls within the semiconductor substrate;
• a dielectric material contacting the bottom surface and the opposing side walls and extending to a top surface that is not above the first recess;
• and
• a pair of second recesses each:
• being within the first recess;
• being defined by a recess surface the majority of which is covered by a storage node;
• being defined by the dielectric material and the semiconductor substrate;
• having therein a cell dielectric contacting the storage node;
• and
• having therein a cell plate upon the cell dielectric, said cell plate contacting the top surface of the dielectric material.

A memory structure including a plurality of memory cells each including a cell plate upon a cell dielectric which is upon a storage node, the memory structure further comprising:

• a substrate having a substrate surface;
• a first recess having opposing side walls extending from the substrate surface;
• a dielectric material within and not extending above the first recess, said dielectric material contacting the opposing side walls;
• and
• a plurality of second recesses each having a recess surface defined by:
• one of the opposing side walls;
• and
• the dielectric material;
• wherein each said storage node is within a respective one of said second recesses and is upon a majority of the recess surface thereof, and wherein each said cell plate contacts the top surface of the dielectric material.