Semiconductor device
AssigneeNEC Corporation
InventorNamiki Sekine
Life of this patent
Estimating the term…
Abstract
In order to precisely estimate a gate length of a MOS transistor in a semiconductor device, the semiconductor device comprises a pair of MOS transistors having different gate lengths. A threshold voltage difference between the MOS transistors is measured by flowing the same amount of current through each of the MOS transistors. The gate length of the MOS transistor can be precisely estimated from the threshold voltage difference thus obtained.
Claims9
A semiconductor device, comprising:
- a plurality of checking patterns, each of the plurality of checking patterns including a first MOS transistor of a first carrier type, having one of a plurality of gate lengths, L, and a second MOS transistor of the first carrier type, having one of a plurality of gate lengths, L+dL, connected in parallel, wherein
- an output, resulting from a current of a MOS transistor of a second carrier type that is applied to the first and second MOS transistors, provides a threshold voltage difference between the first and second MOS transistors of at least one of the plurality of checking patterns.
A semiconductor device, comprising:
- a plurality of checking patterns, each of the plurality of checking patterns including a first MOS transistor of a first carrier type, having one of a plurality of gate lengths, L, and a second MOS transistor of the first carrier type, having one of a plurality of gate lengths, L+dL, connected in parallel, wherein
- a threshold voltage difference from at least one of the plurality of checking patterns results from an application of a predetermined current from a current mirror of MOS transistors of a second carrier type to the first and second MOS transistors to the at least one of the plurality of checking patterns.
A semiconductor device having a checking pattern composed of a high voltage terminal, a low voltage terminal, a current mirror circuit having a pair of current paths flowing the same amount of current, one end of each of said pair of current paths being connected to one of said high voltage terminal and said low voltage terminal, a first MOS transistor having a source-drain path connected between the other end of one of said pair of current paths and the other of said high voltage terminal and said low voltage terminal, said first MOS transistor having a gate connected to a drain of said first MOS transistor, and a second MOS transistor of the same channel type as that of said first MOS transistor, said second MOS transistor having a source-drain path connected between the other end of the other of said pair of current paths and the other of said high voltage terminal and said low voltage terminal, said second MOS transistor having a gate connected to a drain of said second MOS transistor, said second MOS transistor having a gate length different from that of said first MOS transistor so that when the same amount of current is flowed through each of said first and second MOS transistors by said current mirror circuit, a voltage difference appears between said gate of said first MOS transistor and said gate of said second MOS transistor.
A semiconductor device, having N-type and P-type MOS transistors, that forms a checking pattern, comprising:
- a pair of MOS transistors of a first type, configured as a current mirror;
- a first MOS transistor of a second type, having a gate length, L;
- a second MOS transistor of the second type, having a gate length, L+dL, wherein a drain and a gate of the first MOS transistor are connected to a drain of one of the pair of MOS transistors, and a drain and a gate of the second MOS transistor are connected to a drain of another one of the pair of MOS transistors.
Dependencies are inferred from the claim text.